; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn < %s 2>&1 | FileCheck -check-prefix=GCN %s

; It is not illegal anymore because the SGPRs with divergent values are added with readfirstlane 
; instruction in inline asm.
define amdgpu_kernel void @illegal_vgpr_to_sgpr_copy_i32() #0 {
; GCN-LABEL: illegal_vgpr_to_sgpr_copy_i32:
; GCN:       ; %bb.0:
; GCN-NEXT:    ;;#ASMSTART
; GCN-NEXT:    ; def v1
; GCN-NEXT:    ;;#ASMEND
; GCN-NEXT:    v_readfirstlane_b32 s9, v1
; GCN-NEXT:    ;;#ASMSTART
; GCN-NEXT:    ; use s9
; GCN-NEXT:    ;;#ASMEND
; GCN-NEXT:    s_endpgm
  %vgpr = call i32 asm sideeffect "; def $0", "=${v1}"()
  call void asm sideeffect "; use $0", "${s9}"(i32 %vgpr)
  ret void
}

define amdgpu_kernel void @illegal_vgpr_to_sgpr_copy_v2i32() #0 {
; GCN-LABEL: illegal_vgpr_to_sgpr_copy_v2i32:
; GCN:       ; %bb.0:
; GCN-NEXT:    ;;#ASMSTART
; GCN-NEXT:    ; def v[0:1]
; GCN-NEXT:    ;;#ASMEND
; GCN-NEXT:    v_readfirstlane_b32 s11, v1
; GCN-NEXT:    v_readfirstlane_b32 s10, v0
; GCN-NEXT:    ;;#ASMSTART
; GCN-NEXT:    ; use s[10:11]
; GCN-NEXT:    ;;#ASMEND
; GCN-NEXT:    s_endpgm
  %vgpr = call <2 x i32> asm sideeffect "; def $0", "=${v[0:1]}"()
  call void asm sideeffect "; use $0", "${s[10:11]}"(<2 x i32> %vgpr)
  ret void
}

define amdgpu_kernel void @illegal_vgpr_to_sgpr_copy_v4i32() #0 {
; GCN-LABEL: illegal_vgpr_to_sgpr_copy_v4i32:
; GCN:       ; %bb.0:
; GCN-NEXT:    ;;#ASMSTART
; GCN-NEXT:    ; def v[0:3]
; GCN-NEXT:    ;;#ASMEND
; GCN-NEXT:    v_readfirstlane_b32 s11, v3
; GCN-NEXT:    v_readfirstlane_b32 s10, v2
; GCN-NEXT:    v_readfirstlane_b32 s9, v1
; GCN-NEXT:    v_readfirstlane_b32 s8, v0
; GCN-NEXT:    ;;#ASMSTART
; GCN-NEXT:    ; use s[8:11]
; GCN-NEXT:    ;;#ASMEND
; GCN-NEXT:    s_endpgm
  %vgpr = call <4 x i32> asm sideeffect "; def $0", "=${v[0:3]}"()
  call void asm sideeffect "; use $0", "${s[8:11]}"(<4 x i32> %vgpr)
  ret void
}

define amdgpu_kernel void @illegal_vgpr_to_sgpr_copy_v8i32() #0 {
; GCN-LABEL: illegal_vgpr_to_sgpr_copy_v8i32:
; GCN:       ; %bb.0:
; GCN-NEXT:    ;;#ASMSTART
; GCN-NEXT:    ; def v[0:7]
; GCN-NEXT:    ;;#ASMEND
; GCN-NEXT:    v_readfirstlane_b32 s15, v7
; GCN-NEXT:    v_readfirstlane_b32 s14, v6
; GCN-NEXT:    v_readfirstlane_b32 s13, v5
; GCN-NEXT:    v_readfirstlane_b32 s12, v4
; GCN-NEXT:    v_readfirstlane_b32 s11, v3
; GCN-NEXT:    v_readfirstlane_b32 s10, v2
; GCN-NEXT:    v_readfirstlane_b32 s9, v1
; GCN-NEXT:    v_readfirstlane_b32 s8, v0
; GCN-NEXT:    ;;#ASMSTART
; GCN-NEXT:    ; use s[8:15]
; GCN-NEXT:    ;;#ASMEND
; GCN-NEXT:    s_endpgm
  %vgpr = call <8 x i32> asm sideeffect "; def $0", "=${v[0:7]}"()
  call void asm sideeffect "; use $0", "${s[8:15]}"(<8 x i32> %vgpr)
  ret void
}

define amdgpu_kernel void @illegal_vgpr_to_sgpr_copy_v16i32() #0 {
; GCN-LABEL: illegal_vgpr_to_sgpr_copy_v16i32:
; GCN:       ; %bb.0:
; GCN-NEXT:    ;;#ASMSTART
; GCN-NEXT:    ; def v[0:15]
; GCN-NEXT:    ;;#ASMEND
; GCN-NEXT:    v_readfirstlane_b32 s31, v15
; GCN-NEXT:    v_readfirstlane_b32 s30, v14
; GCN-NEXT:    v_readfirstlane_b32 s29, v13
; GCN-NEXT:    v_readfirstlane_b32 s28, v12
; GCN-NEXT:    v_readfirstlane_b32 s27, v11
; GCN-NEXT:    v_readfirstlane_b32 s26, v10
; GCN-NEXT:    v_readfirstlane_b32 s25, v9
; GCN-NEXT:    v_readfirstlane_b32 s24, v8
; GCN-NEXT:    v_readfirstlane_b32 s23, v7
; GCN-NEXT:    v_readfirstlane_b32 s22, v6
; GCN-NEXT:    v_readfirstlane_b32 s21, v5
; GCN-NEXT:    v_readfirstlane_b32 s20, v4
; GCN-NEXT:    v_readfirstlane_b32 s19, v3
; GCN-NEXT:    v_readfirstlane_b32 s18, v2
; GCN-NEXT:    v_readfirstlane_b32 s17, v1
; GCN-NEXT:    v_readfirstlane_b32 s16, v0
; GCN-NEXT:    ;;#ASMSTART
; GCN-NEXT:    ; use s[16:31]
; GCN-NEXT:    ;;#ASMEND
; GCN-NEXT:    s_endpgm
  %vgpr = call <16 x i32> asm sideeffect "; def $0", "=${v[0:15]}"()
  call void asm sideeffect "; use $0", "${s[16:31]}"(<16 x i32> %vgpr)
  ret void
}

define amdgpu_kernel void @illegal_agpr_to_sgpr_copy_i32() #1 {
; GCN-LABEL: illegal_agpr_to_sgpr_copy_i32:
; GCN:       ; %bb.0:
; GCN-NEXT:    ;;#ASMSTART
; GCN-NEXT:    ; def a1
; GCN-NEXT:    ;;#ASMEND
; GCN-NEXT:    v_accvgpr_read_b32 v0, a1
; GCN-NEXT:    v_readfirstlane_b32 s9, v0
; GCN-NEXT:    ;;#ASMSTART
; GCN-NEXT:    ; use s9
; GCN-NEXT:    ;;#ASMEND
; GCN-NEXT:    s_endpgm
  %agpr = call i32 asm sideeffect "; def $0", "=${a1}"()
  call void asm sideeffect "; use $0", "${s9}"(i32 %agpr)
  ret void
}

define amdgpu_kernel void @illegal_agpr_to_sgpr_copy_v2i32() #1 {
; GCN-LABEL: illegal_agpr_to_sgpr_copy_v2i32:
; GCN:       ; %bb.0:
; GCN-NEXT:    ;;#ASMSTART
; GCN-NEXT:    ; def a[0:1]
; GCN-NEXT:    ;;#ASMEND
; GCN-NEXT:    v_accvgpr_read_b32 v0, a0
; GCN-NEXT:    v_accvgpr_read_b32 v1, a1
; GCN-NEXT:    v_readfirstlane_b32 s11, v1
; GCN-NEXT:    v_readfirstlane_b32 s10, v0
; GCN-NEXT:    ;;#ASMSTART
; GCN-NEXT:    ; use s[10:11]
; GCN-NEXT:    ;;#ASMEND
; GCN-NEXT:    s_endpgm
  %vgpr = call <2 x i32> asm sideeffect "; def $0", "=${a[0:1]}"()
  call void asm sideeffect "; use $0", "${s[10:11]}"(<2 x i32> %vgpr)
  ret void
}

attributes #0 = { nounwind }
attributes #1 = { nounwind "target-cpu"="gfx908" }