; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG-REAL16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG-FAKE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-REAL16 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-FAKE16 %s

declare i16 @llvm.amdgcn.cvt.pk.bf8.f16(<2 x half>)
declare i16 @llvm.amdgcn.cvt.pk.fp8.f16(<2 x half>)
declare i32 @llvm.amdgcn.cvt.sr.bf8.f16(half, i32, i32, i32)
declare i32 @llvm.amdgcn.cvt.sr.fp8.f16(half, i32, i32, i32)

define amdgpu_ps void @test_cvt_pk_bf8_f16_v(<2 x half> %a, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_bf8_f16_v:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-REAL16-NEXT:    v_cvt_pk_bf8_f16 v0.l, v0
; GFX1250-SDAG-REAL16-NEXT:    global_store_b16 v[2:3], v0, off
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_bf8_f16_v:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_pk_bf8_f16 v0, v0
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b16 v[2:3], v0, off
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_bf8_f16_v:
; GFX1250-GISEL-REAL16:       ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-REAL16-NEXT:    v_nop
; GFX1250-GISEL-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-REAL16-NEXT:    v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-REAL16-NEXT:    v_cvt_pk_bf8_f16 v0.l, v0
; GFX1250-GISEL-REAL16-NEXT:    global_store_b16 v[4:5], v0, off
; GFX1250-GISEL-REAL16-NEXT:    s_endpgm
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_bf8_f16_v:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-FAKE16-NEXT:    v_nop
; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_pk_bf8_f16 v0, v0
; GFX1250-GISEL-FAKE16-NEXT:    global_store_b16 v[4:5], v0, off
; GFX1250-GISEL-FAKE16-NEXT:    s_endpgm
  %cvt = tail call i16 @llvm.amdgcn.cvt.pk.bf8.f16(<2 x half> %a)
  store i16 %cvt, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @test_cvt_pk_bf8_f16_s(<2 x half> inreg %a, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_bf8_f16_s:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    v_cvt_pk_bf8_f16 v2.l, s0
; GFX1250-SDAG-REAL16-NEXT:    global_store_b16 v[0:1], v2, off
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_bf8_f16_s:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_pk_bf8_f16 v2, s0
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b16 v[0:1], v2, off
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_bf8_f16_s:
; GFX1250-GISEL-REAL16:       ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-REAL16-NEXT:    v_nop
; GFX1250-GISEL-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-REAL16-NEXT:    v_cvt_pk_bf8_f16 v2.l, s0
; GFX1250-GISEL-REAL16-NEXT:    global_store_b16 v[0:1], v2, off
; GFX1250-GISEL-REAL16-NEXT:    s_endpgm
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_bf8_f16_s:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-FAKE16-NEXT:    v_nop
; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_pk_bf8_f16 v2, s0
; GFX1250-GISEL-FAKE16-NEXT:    global_store_b16 v[0:1], v2, off
; GFX1250-GISEL-FAKE16-NEXT:    s_endpgm
  %cvt = tail call i16 @llvm.amdgcn.cvt.pk.bf8.f16(<2 x half> %a)
  store i16 %cvt, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @test_cvt_pk_bf8_f16_l(ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_bf8_f16_l:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    v_cvt_pk_bf8_f16 v2.l, 0x56400000
; GFX1250-SDAG-REAL16-NEXT:    global_store_b16 v[0:1], v2, off
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_bf8_f16_l:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_pk_bf8_f16 v2, 0x56400000
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b16 v[0:1], v2, off
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_bf8_f16_l:
; GFX1250-GISEL-REAL16:       ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-REAL16-NEXT:    v_nop
; GFX1250-GISEL-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-REAL16-NEXT:    v_cvt_pk_bf8_f16 v2.l, 0x56400000
; GFX1250-GISEL-REAL16-NEXT:    global_store_b16 v[0:1], v2, off
; GFX1250-GISEL-REAL16-NEXT:    s_endpgm
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_bf8_f16_l:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-FAKE16-NEXT:    v_nop
; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_pk_bf8_f16 v2, 0x56400000
; GFX1250-GISEL-FAKE16-NEXT:    global_store_b16 v[0:1], v2, off
; GFX1250-GISEL-FAKE16-NEXT:    s_endpgm
  %cvt = tail call i16 @llvm.amdgcn.cvt.pk.bf8.f16(<2 x half> <half 0.0, half 100.0>)
  store i16 %cvt, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @test_cvt_pk_fp8_f16_v(<2 x half> %a, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_fp8_f16_v:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-REAL16-NEXT:    v_cvt_pk_fp8_f16 v0.l, v0
; GFX1250-SDAG-REAL16-NEXT:    global_store_b16 v[2:3], v0, off
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_fp8_f16_v:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_pk_fp8_f16 v0, v0
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b16 v[2:3], v0, off
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_fp8_f16_v:
; GFX1250-GISEL-REAL16:       ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-REAL16-NEXT:    v_nop
; GFX1250-GISEL-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-REAL16-NEXT:    v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-REAL16-NEXT:    v_cvt_pk_fp8_f16 v0.l, v0
; GFX1250-GISEL-REAL16-NEXT:    global_store_b16 v[4:5], v0, off
; GFX1250-GISEL-REAL16-NEXT:    s_endpgm
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_fp8_f16_v:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-FAKE16-NEXT:    v_nop
; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_pk_fp8_f16 v0, v0
; GFX1250-GISEL-FAKE16-NEXT:    global_store_b16 v[4:5], v0, off
; GFX1250-GISEL-FAKE16-NEXT:    s_endpgm
  %cvt = tail call i16 @llvm.amdgcn.cvt.pk.fp8.f16(<2 x half> %a)
  store i16 %cvt, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @test_cvt_pk_fp8_f16_s(<2 x half> inreg %a, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_fp8_f16_s:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    v_cvt_pk_fp8_f16 v2.l, s0
; GFX1250-SDAG-REAL16-NEXT:    global_store_b16 v[0:1], v2, off
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_fp8_f16_s:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_pk_fp8_f16 v2, s0
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b16 v[0:1], v2, off
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_fp8_f16_s:
; GFX1250-GISEL-REAL16:       ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-REAL16-NEXT:    v_nop
; GFX1250-GISEL-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-REAL16-NEXT:    v_cvt_pk_fp8_f16 v2.l, s0
; GFX1250-GISEL-REAL16-NEXT:    global_store_b16 v[0:1], v2, off
; GFX1250-GISEL-REAL16-NEXT:    s_endpgm
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_fp8_f16_s:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-FAKE16-NEXT:    v_nop
; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_pk_fp8_f16 v2, s0
; GFX1250-GISEL-FAKE16-NEXT:    global_store_b16 v[0:1], v2, off
; GFX1250-GISEL-FAKE16-NEXT:    s_endpgm
  %cvt = tail call i16 @llvm.amdgcn.cvt.pk.fp8.f16(<2 x half> %a)
  store i16 %cvt, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @test_cvt_pk_fp8_f16_l(ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_fp8_f16_l:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    v_cvt_pk_fp8_f16 v2.l, 0x56400000
; GFX1250-SDAG-REAL16-NEXT:    global_store_b16 v[0:1], v2, off
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_fp8_f16_l:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_pk_fp8_f16 v2, 0x56400000
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b16 v[0:1], v2, off
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_fp8_f16_l:
; GFX1250-GISEL-REAL16:       ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-REAL16-NEXT:    v_nop
; GFX1250-GISEL-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-REAL16-NEXT:    v_cvt_pk_fp8_f16 v2.l, 0x56400000
; GFX1250-GISEL-REAL16-NEXT:    global_store_b16 v[0:1], v2, off
; GFX1250-GISEL-REAL16-NEXT:    s_endpgm
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_fp8_f16_l:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-FAKE16-NEXT:    v_nop
; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_pk_fp8_f16 v2, 0x56400000
; GFX1250-GISEL-FAKE16-NEXT:    global_store_b16 v[0:1], v2, off
; GFX1250-GISEL-FAKE16-NEXT:    s_endpgm
  %cvt = tail call i16 @llvm.amdgcn.cvt.pk.fp8.f16(<2 x half> <half 0.0, half 100.0>)
  store i16 %cvt, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @test_cvt_sr_bf8_f16_byte0(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_bf8_f16_byte0:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-REAL16-NEXT:    v_cvt_sr_bf8_f16 v2, v0.l, v1
; GFX1250-SDAG-REAL16-NEXT:    global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte0:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_sr_bf8_f16 v2, v0, v1
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_bf8_f16_byte0:
; GFX1250-GISEL-REAL16:       ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-REAL16-NEXT:    v_nop
; GFX1250-GISEL-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-REAL16-NEXT:    v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-REAL16-NEXT:    v_cvt_sr_bf8_f16 v2, v0.l, v1
; GFX1250-GISEL-REAL16-NEXT:    global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-REAL16-NEXT:    s_endpgm
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte0:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-FAKE16-NEXT:    v_nop
; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_sr_bf8_f16 v2, v0, v1
; GFX1250-GISEL-FAKE16-NEXT:    global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-FAKE16-NEXT:    s_endpgm
  %cvt = tail call i32 @llvm.amdgcn.cvt.sr.bf8.f16(half %a, i32 %sr, i32 %old, i32 0)
  store i32 %cvt, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @test_cvt_sr_bf8_f16_byte1(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_bf8_f16_byte1:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-REAL16-NEXT:    v_cvt_sr_bf8_f16 v2, v0.l, v1 byte_sel:1
; GFX1250-SDAG-REAL16-NEXT:    global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte1:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:1
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_bf8_f16_byte1:
; GFX1250-GISEL-REAL16:       ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-REAL16-NEXT:    v_nop
; GFX1250-GISEL-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-REAL16-NEXT:    v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-REAL16-NEXT:    v_cvt_sr_bf8_f16 v2, v0.l, v1 byte_sel:1
; GFX1250-GISEL-REAL16-NEXT:    global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-REAL16-NEXT:    s_endpgm
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte1:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-FAKE16-NEXT:    v_nop
; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:1
; GFX1250-GISEL-FAKE16-NEXT:    global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-FAKE16-NEXT:    s_endpgm
  %cvt = tail call i32 @llvm.amdgcn.cvt.sr.bf8.f16(half %a, i32 %sr, i32 %old, i32 1)
  store i32 %cvt, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @test_cvt_sr_bf8_f16_byte2(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_bf8_f16_byte2:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-REAL16-NEXT:    v_cvt_sr_bf8_f16 v2, v0.l, v1 byte_sel:2
; GFX1250-SDAG-REAL16-NEXT:    global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte2:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:2
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_bf8_f16_byte2:
; GFX1250-GISEL-REAL16:       ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-REAL16-NEXT:    v_nop
; GFX1250-GISEL-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-REAL16-NEXT:    v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-REAL16-NEXT:    v_cvt_sr_bf8_f16 v2, v0.l, v1 byte_sel:2
; GFX1250-GISEL-REAL16-NEXT:    global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-REAL16-NEXT:    s_endpgm
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte2:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-FAKE16-NEXT:    v_nop
; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:2
; GFX1250-GISEL-FAKE16-NEXT:    global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-FAKE16-NEXT:    s_endpgm
  %cvt = tail call i32 @llvm.amdgcn.cvt.sr.bf8.f16(half %a, i32 %sr, i32 %old, i32 2)
  store i32 %cvt, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @test_cvt_sr_bf8_f16_byte3(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_bf8_f16_byte3:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-REAL16-NEXT:    v_cvt_sr_bf8_f16 v2, v0.l, v1 byte_sel:3
; GFX1250-SDAG-REAL16-NEXT:    global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte3:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:3
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_bf8_f16_byte3:
; GFX1250-GISEL-REAL16:       ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-REAL16-NEXT:    v_nop
; GFX1250-GISEL-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-REAL16-NEXT:    v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-REAL16-NEXT:    v_cvt_sr_bf8_f16 v2, v0.l, v1 byte_sel:3
; GFX1250-GISEL-REAL16-NEXT:    global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-REAL16-NEXT:    s_endpgm
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte3:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-FAKE16-NEXT:    v_nop
; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:3
; GFX1250-GISEL-FAKE16-NEXT:    global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-FAKE16-NEXT:    s_endpgm
  %cvt = tail call i32 @llvm.amdgcn.cvt.sr.bf8.f16(half %a, i32 %sr, i32 %old, i32 3)
  store i32 %cvt, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @test_cvt_sr_bf8_f16_hi_byte0(<2 x half> %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_bf8_f16_hi_byte0:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-REAL16-NEXT:    v_cvt_sr_bf8_f16 v2, v0.h, v1
; GFX1250-SDAG-REAL16-NEXT:    global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_bf8_f16_hi_byte0:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v5, v4 :: v_dual_lshrrev_b32 v0, 16, v0
; GFX1250-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v4, v3
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_sr_bf8_f16 v2, v0, v1
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_bf8_f16_hi_byte0:
; GFX1250-GISEL-REAL16:       ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-REAL16-NEXT:    v_nop
; GFX1250-GISEL-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-REAL16-NEXT:    v_dual_lshrrev_b32 v0, 16, v0 :: v_dual_mov_b32 v6, v3
; GFX1250-GISEL-REAL16-NEXT:    v_mov_b32_e32 v7, v4
; GFX1250-GISEL-REAL16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1250-GISEL-REAL16-NEXT:    v_cvt_sr_bf8_f16 v2, v0.l, v1
; GFX1250-GISEL-REAL16-NEXT:    global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-REAL16-NEXT:    s_endpgm
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_bf8_f16_hi_byte0:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-FAKE16-NEXT:    v_nop
; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_lshrrev_b32 v0, 16, v0 :: v_dual_mov_b32 v6, v3
; GFX1250-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v7, v4
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_sr_bf8_f16 v2, v0, v1
; GFX1250-GISEL-FAKE16-NEXT:    global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-FAKE16-NEXT:    s_endpgm
  %a.1 = extractelement <2 x half> %a, i32 1
  %cvt = tail call i32 @llvm.amdgcn.cvt.sr.bf8.f16(half %a.1, i32 %sr, i32 %old, i32 0)
  store i32 %cvt, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @test_cvt_sr_fp8_f16_byte0(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_fp8_f16_byte0:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-REAL16-NEXT:    v_cvt_sr_fp8_f16 v2, v0.l, v1
; GFX1250-SDAG-REAL16-NEXT:    global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte0:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_sr_fp8_f16 v2, v0, v1
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_fp8_f16_byte0:
; GFX1250-GISEL-REAL16:       ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-REAL16-NEXT:    v_nop
; GFX1250-GISEL-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-REAL16-NEXT:    v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-REAL16-NEXT:    v_cvt_sr_fp8_f16 v2, v0.l, v1
; GFX1250-GISEL-REAL16-NEXT:    global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-REAL16-NEXT:    s_endpgm
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte0:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-FAKE16-NEXT:    v_nop
; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_sr_fp8_f16 v2, v0, v1
; GFX1250-GISEL-FAKE16-NEXT:    global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-FAKE16-NEXT:    s_endpgm
  %cvt = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f16(half %a, i32 %sr, i32 %old, i32 0)
  store i32 %cvt, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @test_cvt_sr_fp8_f16_byte1(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_fp8_f16_byte1:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-REAL16-NEXT:    v_cvt_sr_fp8_f16 v2, v0.l, v1 byte_sel:1
; GFX1250-SDAG-REAL16-NEXT:    global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte1:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:1
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_fp8_f16_byte1:
; GFX1250-GISEL-REAL16:       ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-REAL16-NEXT:    v_nop
; GFX1250-GISEL-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-REAL16-NEXT:    v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-REAL16-NEXT:    v_cvt_sr_fp8_f16 v2, v0.l, v1 byte_sel:1
; GFX1250-GISEL-REAL16-NEXT:    global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-REAL16-NEXT:    s_endpgm
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte1:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-FAKE16-NEXT:    v_nop
; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:1
; GFX1250-GISEL-FAKE16-NEXT:    global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-FAKE16-NEXT:    s_endpgm
  %cvt = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f16(half %a, i32 %sr, i32 %old, i32 1)
  store i32 %cvt, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @test_cvt_sr_fp8_f16_byte2(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_fp8_f16_byte2:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-REAL16-NEXT:    v_cvt_sr_fp8_f16 v2, v0.l, v1 byte_sel:2
; GFX1250-SDAG-REAL16-NEXT:    global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte2:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:2
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_fp8_f16_byte2:
; GFX1250-GISEL-REAL16:       ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-REAL16-NEXT:    v_nop
; GFX1250-GISEL-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-REAL16-NEXT:    v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-REAL16-NEXT:    v_cvt_sr_fp8_f16 v2, v0.l, v1 byte_sel:2
; GFX1250-GISEL-REAL16-NEXT:    global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-REAL16-NEXT:    s_endpgm
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte2:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-FAKE16-NEXT:    v_nop
; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:2
; GFX1250-GISEL-FAKE16-NEXT:    global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-FAKE16-NEXT:    s_endpgm
  %cvt = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f16(half %a, i32 %sr, i32 %old, i32 2)
  store i32 %cvt, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @test_cvt_sr_fp8_f16_byte3(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_fp8_f16_byte3:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-REAL16-NEXT:    v_cvt_sr_fp8_f16 v2, v0.l, v1 byte_sel:3
; GFX1250-SDAG-REAL16-NEXT:    global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte3:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:3
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_fp8_f16_byte3:
; GFX1250-GISEL-REAL16:       ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-REAL16-NEXT:    v_nop
; GFX1250-GISEL-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-REAL16-NEXT:    v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-REAL16-NEXT:    v_cvt_sr_fp8_f16 v2, v0.l, v1 byte_sel:3
; GFX1250-GISEL-REAL16-NEXT:    global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-REAL16-NEXT:    s_endpgm
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte3:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-FAKE16-NEXT:    v_nop
; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:3
; GFX1250-GISEL-FAKE16-NEXT:    global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-FAKE16-NEXT:    s_endpgm
  %cvt = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f16(half %a, i32 %sr, i32 %old, i32 3)
  store i32 %cvt, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @test_cvt_sr_fp8_f16_hi_byte0(<2 x half> %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_fp8_f16_hi_byte0:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-REAL16-NEXT:    v_cvt_sr_fp8_f16 v2, v0.h, v1
; GFX1250-SDAG-REAL16-NEXT:    global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_fp8_f16_hi_byte0:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v5, v4 :: v_dual_lshrrev_b32 v0, 16, v0
; GFX1250-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v4, v3
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_sr_fp8_f16 v2, v0, v1
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_fp8_f16_hi_byte0:
; GFX1250-GISEL-REAL16:       ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-REAL16-NEXT:    v_nop
; GFX1250-GISEL-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-REAL16-NEXT:    v_dual_lshrrev_b32 v0, 16, v0 :: v_dual_mov_b32 v6, v3
; GFX1250-GISEL-REAL16-NEXT:    v_mov_b32_e32 v7, v4
; GFX1250-GISEL-REAL16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1250-GISEL-REAL16-NEXT:    v_cvt_sr_fp8_f16 v2, v0.l, v1
; GFX1250-GISEL-REAL16-NEXT:    global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-REAL16-NEXT:    s_endpgm
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_fp8_f16_hi_byte0:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-FAKE16-NEXT:    v_nop
; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_lshrrev_b32 v0, 16, v0 :: v_dual_mov_b32 v6, v3
; GFX1250-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v7, v4
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_sr_fp8_f16 v2, v0, v1
; GFX1250-GISEL-FAKE16-NEXT:    global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-FAKE16-NEXT:    s_endpgm
  %a.1 = extractelement <2 x half> %a, i32 1
  %cvt = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f16(half %a.1, i32 %sr, i32 %old, i32 0)
  store i32 %cvt, ptr addrspace(1) %out
  ret void
}

;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX1250: {{.*}}