; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --global-isel=0 -mtriple=amdgcn -mcpu=tahiti %s -o - | FileCheck %s
; RUN: llc --global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti %s -o - | FileCheck %s
; RUN: llc --global-isel=0 -mtriple=amdgcn -mcpu=tonga %s -o - | FileCheck %s
; RUN: llc --global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga %s -o - | FileCheck %s
; RUN: llc --global-isel=0 -mtriple=amdgcn -mcpu=gfx90a %s -o - | FileCheck %s
; RUN: llc --global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx90a %s -o - | FileCheck %s

declare float @llvm.amdgcn.cvt.off.f32.i4(i32)

define amdgpu_cs float @cvt_var(i32 %a) {
; CHECK-LABEL: cvt_var:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    v_cvt_off_f32_i4_e32 v0, v0
; CHECK-NEXT:    ; return to shader part epilog
  %ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 %a)
  ret float %ret
}

define amdgpu_ps float @cvt_var_s(i32 inreg %a) {
; CHECK-LABEL: cvt_var_s:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    v_cvt_off_f32_i4_e32 v0, s0
; CHECK-NEXT:    ; return to shader part epilog
  %ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 %a)
  ret float %ret
}

define amdgpu_cs float @cvt_imm() {
; CHECK-LABEL: cvt_imm:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    v_cvt_off_f32_i4_e32 v0, 4
; CHECK-NEXT:    ; return to shader part epilog
  %ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 4)
  ret float %ret
}