; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-SDAG %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-GISEL %s

declare <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.bf16(<8 x bfloat> %src, float %scale)
declare <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.bf16(<8 x bfloat> %src, float %scale)
declare <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f16(<8 x half> %src, float %scale)
declare <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f16(<8 x half> %src, float %scale)
declare <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f32(<8 x float> %src, float %scale)
declare <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f32(<8 x float> %src, float %scale)
declare i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f32(<8 x float> %src, float %scale)
declare i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f16(<8 x half> %src, float %scale)
declare i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.bf16(<8 x bfloat> %src, float %scale)

define amdgpu_ps void @test_scalef32_pk8_fp8_bf16_vv(<8 x bfloat> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_bf16_vv:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_pk8_fp8_bf16 v[8:9], v[0:3], v4
; GFX1250-SDAG-NEXT:    global_store_b64 v[6:7], v[8:9], off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_bf16_vv:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_pk8_fp8_bf16 v[8:9], v[0:3], v4
; GFX1250-GISEL-NEXT:    global_store_b64 v[6:7], v[8:9], off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.bf16(<8 x bfloat> %src, float %scale)
  store <2 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_pk8_fp8_bf16_sl(<8 x bfloat> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_bf16_sl:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_pk8_fp8_bf16 v[6:7], v[2:5], 0x42c80000
; GFX1250-SDAG-NEXT:    global_store_b64 v[0:1], v[6:7], off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_bf16_sl:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_pk8_fp8_bf16 v[6:7], v[2:5], 0x42c80000
; GFX1250-GISEL-NEXT:    global_store_b64 v[0:1], v[6:7], off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.bf16(<8 x bfloat> %src, float 100.0)
  store <2 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_pk8_bf8_bf16_vv(<8 x bfloat> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_bf16_vv:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_pk8_bf8_bf16 v[8:9], v[0:3], v4
; GFX1250-SDAG-NEXT:    global_store_b64 v[6:7], v[8:9], off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_bf16_vv:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_pk8_bf8_bf16 v[8:9], v[0:3], v4
; GFX1250-GISEL-NEXT:    global_store_b64 v[6:7], v[8:9], off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.bf16(<8 x bfloat> %src, float %scale)
  store <2 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_pk8_bf8_bf16_sl(<8 x bfloat> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_bf16_sl:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_pk8_bf8_bf16 v[6:7], v[2:5], 0x42c80000
; GFX1250-SDAG-NEXT:    global_store_b64 v[0:1], v[6:7], off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_bf16_sl:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_pk8_bf8_bf16 v[6:7], v[2:5], 0x42c80000
; GFX1250-GISEL-NEXT:    global_store_b64 v[0:1], v[6:7], off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.bf16(<8 x bfloat> %src, float 100.0)
  store <2 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_pk8_fp8_f16_vv(<8 x half> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_f16_vv:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_pk8_fp8_f16 v[8:9], v[0:3], v4
; GFX1250-SDAG-NEXT:    global_store_b64 v[6:7], v[8:9], off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_f16_vv:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v9, v6
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_pk8_fp8_f16 v[6:7], v[0:3], v4
; GFX1250-GISEL-NEXT:    global_store_b64 v[8:9], v[6:7], off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f16(<8 x half> %src, float %scale)
  store <2 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_pk8_fp8_f16_sl(<8 x half> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_f16_sl:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_pk8_fp8_f16 v[6:7], v[2:5], 0x42c80000
; GFX1250-SDAG-NEXT:    global_store_b64 v[0:1], v[6:7], off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_f16_sl:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[2:3], s[0:1]
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_pk8_fp8_f16 v[6:7], v[2:5], 0x42c80000
; GFX1250-GISEL-NEXT:    global_store_b64 v[0:1], v[6:7], off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f16(<8 x half> %src, float 100.0)
  store <2 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_pk8_bf8_f16_vv(<8 x half> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_f16_vv:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_pk8_bf8_f16 v[8:9], v[0:3], v4
; GFX1250-SDAG-NEXT:    global_store_b64 v[6:7], v[8:9], off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_f16_vv:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v9, v6
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_pk8_bf8_f16 v[6:7], v[0:3], v4
; GFX1250-GISEL-NEXT:    global_store_b64 v[8:9], v[6:7], off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f16(<8 x half> %src, float %scale)
  store <2 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_pk8_bf8_f16_sl(<8 x half> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_f16_sl:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_pk8_bf8_f16 v[6:7], v[2:5], 0x42c80000
; GFX1250-SDAG-NEXT:    global_store_b64 v[0:1], v[6:7], off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_f16_sl:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[2:3], s[0:1]
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_pk8_bf8_f16 v[6:7], v[2:5], 0x42c80000
; GFX1250-GISEL-NEXT:    global_store_b64 v[0:1], v[6:7], off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f16(<8 x half> %src, float 100.0)
  store <2 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_pk8_bf8_f32_vv(<8 x float> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_f32_vv:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v10, v9
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_pk8_bf8_f32 v[12:13], v[0:7], v8
; GFX1250-SDAG-NEXT:    global_store_b64 v[10:11], v[12:13], off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_f32_vv:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v12, v9 :: v_dual_mov_b32 v13, v10
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[0:7], v8
; GFX1250-GISEL-NEXT:    global_store_b64 v[12:13], v[10:11], off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f32(<8 x float> %src, float %scale)
  store <2 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_pk8_bf8_f32_sl(<8 x float> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_f32_sl:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[2:9], 0x42c80000
; GFX1250-SDAG-NEXT:    global_store_b64 v[0:1], v[10:11], off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_f32_sl:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[6:7], s[4:5]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[2:3], s[0:1]
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[2:9], 0x42c80000
; GFX1250-GISEL-NEXT:    global_store_b64 v[0:1], v[10:11], off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f32(<8 x float> %src, float 100.0)
  store <2 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_pk8_fp8_f32_vv(<8 x float> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_f32_vv:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v10, v9
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_pk8_fp8_f32 v[12:13], v[0:7], v8
; GFX1250-SDAG-NEXT:    global_store_b64 v[10:11], v[12:13], off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_f32_vv:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v12, v9 :: v_dual_mov_b32 v13, v10
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[0:7], v8
; GFX1250-GISEL-NEXT:    global_store_b64 v[12:13], v[10:11], off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f32(<8 x float> %src, float %scale)
  store <2 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_pk8_fp8_f32_sl(<8 x float> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_f32_sl:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[2:9], 0x42c80000
; GFX1250-SDAG-NEXT:    global_store_b64 v[0:1], v[10:11], off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_f32_sl:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[6:7], s[4:5]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[2:3], s[0:1]
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[2:9], 0x42c80000
; GFX1250-GISEL-NEXT:    global_store_b64 v[0:1], v[10:11], off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f32(<8 x float> %src, float 100.0)
  store <2 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_pk8_fp4_f32_vv(<8 x float> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_f32_vv:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v10, v9
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_pk8_fp4_f32 v9, v[0:7], v8
; GFX1250-SDAG-NEXT:    global_store_b32 v[10:11], v9, off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_f32_vv:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v12, v9 :: v_dual_mov_b32 v13, v10
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_pk8_fp4_f32 v9, v[0:7], v8
; GFX1250-GISEL-NEXT:    global_store_b32 v[12:13], v9, off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f32(<8 x float> %src, float %scale)
  store i32 %cvt, ptr addrspace(1) %out, align 4
  ret void
}

define amdgpu_ps void @test_scalef32_pk8_fp4_f32_sl(<8 x float> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_f32_sl:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_pk8_fp4_f32 v10, v[2:9], 0x42c80000
; GFX1250-SDAG-NEXT:    global_store_b32 v[0:1], v10, off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_f32_sl:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[6:7], s[4:5]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[2:3], s[0:1]
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_pk8_fp4_f32 v10, v[2:9], 0x42c80000
; GFX1250-GISEL-NEXT:    global_store_b32 v[0:1], v10, off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f32(<8 x float> %src, float 100.0)
  store i32 %cvt, ptr addrspace(1) %out, align 4
  ret void
}

define amdgpu_ps void @test_scalef32_pk8_fp4_f16_vv(<8 x half> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_f16_vv:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_pk8_fp4_f16 v5, v[0:3], v4
; GFX1250-SDAG-NEXT:    global_store_b32 v[6:7], v5, off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_f16_vv:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v9, v6
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_pk8_fp4_f16 v5, v[0:3], v4
; GFX1250-GISEL-NEXT:    global_store_b32 v[8:9], v5, off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f16(<8 x half> %src, float %scale)
  store i32 %cvt, ptr addrspace(1) %out, align 4
  ret void
}

define amdgpu_ps void @test_scalef32_pk8_fp4_f16_sl(<8 x half> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_f16_sl:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_pk8_fp4_f16 v6, v[2:5], 0x42c80000
; GFX1250-SDAG-NEXT:    global_store_b32 v[0:1], v6, off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_f16_sl:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[2:3], s[0:1]
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_pk8_fp4_f16 v6, v[2:5], 0x42c80000
; GFX1250-GISEL-NEXT:    global_store_b32 v[0:1], v6, off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f16(<8 x half> %src, float 100.0)
  store i32 %cvt, ptr addrspace(1) %out, align 4
  ret void
}

define amdgpu_ps void @test_scalef32_pk8_fp4_bf16_vv(<8 x bfloat> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_bf16_vv:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_pk8_fp4_bf16 v5, v[0:3], v4
; GFX1250-SDAG-NEXT:    global_store_b32 v[6:7], v5, off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_bf16_vv:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_pk8_fp4_bf16 v5, v[0:3], v4
; GFX1250-GISEL-NEXT:    global_store_b32 v[6:7], v5, off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.bf16(<8 x bfloat> %src, float %scale)
  store i32 %cvt, ptr addrspace(1) %out, align 4
  ret void
}

define amdgpu_ps void @test_scalef32_pk8_fp4_bf16_sl(<8 x bfloat> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_bf16_sl:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_pk8_fp4_bf16 v6, v[2:5], 0x42c80000
; GFX1250-SDAG-NEXT:    global_store_b32 v[0:1], v6, off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_bf16_sl:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_pk8_fp4_bf16 v6, v[2:5], 0x42c80000
; GFX1250-GISEL-NEXT:    global_store_b32 v[0:1], v6, off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.bf16(<8 x bfloat> %src, float 100.0)
  store i32 %cvt, ptr addrspace(1) %out, align 4
  ret void
}