; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250 %s
; RUN: llc -global-isel=0 -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn -mcpu=gfx1310 < %s | FileCheck -check-prefixes=GFX13 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn -mcpu=gfx1310 < %s | FileCheck -check-prefixes=GFX13 %s

define i32 @v_permlane_idx_gen_b32_vs(i32 %src0, i32 %src1) {
; GFX1250-LABEL: v_permlane_idx_gen_b32_vs:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_readfirstlane_b32 s0, v1
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_permlane_idx_gen_b32 v0, v0, s0
; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX13-LABEL: v_permlane_idx_gen_b32_vs:
; GFX13:       ; %bb.0:
; GFX13-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX13-NEXT:    s_wait_expcnt 0x0
; GFX13-NEXT:    s_wait_samplecnt 0x0
; GFX13-NEXT:    s_wait_bvhcnt 0x0
; GFX13-NEXT:    s_wait_kmcnt 0x0
; GFX13-NEXT:    v_readfirstlane_b32 s0, v1
; GFX13-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX13-NEXT:    v_permlane_idx_gen_b32 v0, v0, s0
; GFX13-NEXT:    s_set_pc_i64 s[30:31]
  %v = call i32 @llvm.amdgcn.permlane.idx.gen(i32 %src0, i32 %src1)
  ret i32 %v
}

define i32 @v_permlane_idx_gen_b32_vi(i32 %src0) {
; GFX1250-LABEL: v_permlane_idx_gen_b32_vi:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_permlane_idx_gen_b32 v0, v0, 1
; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX13-LABEL: v_permlane_idx_gen_b32_vi:
; GFX13:       ; %bb.0:
; GFX13-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX13-NEXT:    s_wait_expcnt 0x0
; GFX13-NEXT:    s_wait_samplecnt 0x0
; GFX13-NEXT:    s_wait_bvhcnt 0x0
; GFX13-NEXT:    s_wait_kmcnt 0x0
; GFX13-NEXT:    v_permlane_idx_gen_b32 v0, v0, 1
; GFX13-NEXT:    s_set_pc_i64 s[30:31]
  %v = call i32 @llvm.amdgcn.permlane.idx.gen(i32 %src0, i32 1)
  ret i32 %v
}

define i32 @v_permlane_idx_gen_b32_vl(i32 %src0) {
; GFX1250-LABEL: v_permlane_idx_gen_b32_vl:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_permlane_idx_gen_b32 v0, v0, 0x64
; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX13-LABEL: v_permlane_idx_gen_b32_vl:
; GFX13:       ; %bb.0:
; GFX13-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX13-NEXT:    s_wait_expcnt 0x0
; GFX13-NEXT:    s_wait_samplecnt 0x0
; GFX13-NEXT:    s_wait_bvhcnt 0x0
; GFX13-NEXT:    s_wait_kmcnt 0x0
; GFX13-NEXT:    v_permlane_idx_gen_b32 v0, v0, 0x64
; GFX13-NEXT:    s_set_pc_i64 s[30:31]
  %v = call i32 @llvm.amdgcn.permlane.idx.gen(i32 %src0, i32 100)
  ret i32 %v
}

define i32 @v_permlane_idx_gen_b32_vv() {
; GFX1250-LABEL: v_permlane_idx_gen_b32_vv:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_bfe_u32 v0, v31, 10, 10
; GFX1250-NEXT:    v_and_b32_e32 v1, 0x3ff, v31
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT:    v_readfirstlane_b32 s0, v0
; GFX1250-NEXT:    v_permlane_idx_gen_b32 v0, v1, s0
; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX13-LABEL: v_permlane_idx_gen_b32_vv:
; GFX13:       ; %bb.0:
; GFX13-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX13-NEXT:    s_wait_expcnt 0x0
; GFX13-NEXT:    s_wait_samplecnt 0x0
; GFX13-NEXT:    s_wait_bvhcnt 0x0
; GFX13-NEXT:    s_wait_kmcnt 0x0
; GFX13-NEXT:    v_bfe_u32 v0, v31, 10, 10
; GFX13-NEXT:    v_and_b32_e32 v1, 0x3ff, v31
; GFX13-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX13-NEXT:    v_readfirstlane_b32 s0, v0
; GFX13-NEXT:    v_permlane_idx_gen_b32 v0, v1, s0
; GFX13-NEXT:    s_set_pc_i64 s[30:31]
  %tidx = call i32 @llvm.amdgcn.workitem.id.x()
  %tidy = call i32 @llvm.amdgcn.workitem.id.y()
  %v = call i32 @llvm.amdgcn.permlane.idx.gen(i32 %tidx, i32 %tidy)
  ret i32 %v
}