; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefixes=SI %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s
; RUN: llc -mtriple=amdgcn -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=SI-GISEL %s
; RUN: llc -mtriple=amdgcn -global-isel=1 -new-reg-bank-select -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=VI-GISEL %s
; RUN: llc -mtriple=amdgcn -global-isel=1 -new-reg-bank-select -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12-GISEL %s

declare float @llvm.amdgcn.rsq.f32(float) #0
declare double @llvm.amdgcn.rsq.f64(double) #0

define amdgpu_kernel void @rsq_f32(ptr addrspace(1) %out, float %src) #1 {
; SI-LABEL: rsq_f32:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dword s6, s[4:5], 0xb
; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    v_rsq_f32_e32 v0, s6
; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: rsq_f32:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dword s2, s[4:5], 0x2c
; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    v_rsq_f32_e32 v2, s2
; VI-NEXT:    v_mov_b32_e32 v0, s0
; VI-NEXT:    v_mov_b32_e32 v1, s1
; VI-NEXT:    flat_store_dword v[0:1], v2
; VI-NEXT:    s_endpgm
;
; SI-GISEL-LABEL: rsq_f32:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_load_dword s3, s[4:5], 0xb
; SI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-GISEL-NEXT:    s_mov_b32 s2, -1
; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT:    v_rsq_f32_e32 v0, s3
; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT:    s_endpgm
;
; VI-GISEL-LABEL: rsq_f32:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    s_load_dword s2, s[4:5], 0x2c
; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT:    v_rsq_f32_e32 v0, s2
; VI-GISEL-NEXT:    s_mov_b32 s2, -1
; VI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT:    s_endpgm
;
; GFX12-GISEL-LABEL: rsq_f32:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-GISEL-NEXT:    v_mov_b32_e32 v1, 0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    v_s_rsq_f32 s2, s2
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT:    s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, s2
; GFX12-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX12-GISEL-NEXT:    s_endpgm
  %rsq = call float @llvm.amdgcn.rsq.f32(float %src) #0
  store float %rsq, ptr addrspace(1) %out, align 4
  ret void
}

; TODO: Really these should be constant folded
define amdgpu_kernel void @rsq_f32_constant_4.0(ptr addrspace(1) %out) #1 {
; SI-LABEL: rsq_f32_constant_4.0:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    v_rsq_f32_e32 v0, 4.0
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: rsq_f32_constant_4.0:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT:    v_rsq_f32_e32 v2, 4.0
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    v_mov_b32_e32 v0, s0
; VI-NEXT:    v_mov_b32_e32 v1, s1
; VI-NEXT:    flat_store_dword v[0:1], v2
; VI-NEXT:    s_endpgm
;
; SI-GISEL-LABEL: rsq_f32_constant_4.0:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-GISEL-NEXT:    v_rsq_f32_e32 v0, 4.0
; SI-GISEL-NEXT:    s_mov_b32 s2, -1
; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT:    s_endpgm
;
; VI-GISEL-LABEL: rsq_f32_constant_4.0:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-GISEL-NEXT:    v_rsq_f32_e32 v0, 4.0
; VI-GISEL-NEXT:    s_mov_b32 s2, -1
; VI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT:    s_endpgm
;
; GFX12-GISEL-LABEL: rsq_f32_constant_4.0:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-GISEL-NEXT:    v_s_rsq_f32 s2, 4.0
; GFX12-GISEL-NEXT:    s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-GISEL-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX12-GISEL-NEXT:    s_endpgm
  %rsq = call float @llvm.amdgcn.rsq.f32(float 4.0) #0
  store float %rsq, ptr addrspace(1) %out, align 4
  ret void
}

define amdgpu_kernel void @rsq_f32_constant_100.0(ptr addrspace(1) %out) #1 {
; SI-LABEL: rsq_f32_constant_100.0:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    v_rsq_f32_e32 v0, 0x42c80000
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: rsq_f32_constant_100.0:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT:    v_rsq_f32_e32 v2, 0x42c80000
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    v_mov_b32_e32 v0, s0
; VI-NEXT:    v_mov_b32_e32 v1, s1
; VI-NEXT:    flat_store_dword v[0:1], v2
; VI-NEXT:    s_endpgm
;
; SI-GISEL-LABEL: rsq_f32_constant_100.0:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-GISEL-NEXT:    v_rsq_f32_e32 v0, 0x42c80000
; SI-GISEL-NEXT:    s_mov_b32 s2, -1
; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT:    s_endpgm
;
; VI-GISEL-LABEL: rsq_f32_constant_100.0:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-GISEL-NEXT:    v_rsq_f32_e32 v0, 0x42c80000
; VI-GISEL-NEXT:    s_mov_b32 s2, -1
; VI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT:    s_endpgm
;
; GFX12-GISEL-LABEL: rsq_f32_constant_100.0:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-GISEL-NEXT:    v_s_rsq_f32 s2, 0x42c80000
; GFX12-GISEL-NEXT:    s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-GISEL-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX12-GISEL-NEXT:    s_endpgm
  %rsq = call float @llvm.amdgcn.rsq.f32(float 100.0) #0
  store float %rsq, ptr addrspace(1) %out, align 4
  ret void
}

define amdgpu_kernel void @rsq_f64(ptr addrspace(1) %out, double %src) #1 {
; SI-LABEL: rsq_f64:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT:    s_mov_b32 s7, 0xf000
; SI-NEXT:    s_mov_b32 s6, -1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_mov_b32 s4, s0
; SI-NEXT:    s_mov_b32 s5, s1
; SI-NEXT:    v_rsq_f64_e32 v[0:1], s[2:3]
; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: rsq_f64:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    v_rsq_f64_e32 v[0:1], s[2:3]
; VI-NEXT:    v_mov_b32_e32 v2, s0
; VI-NEXT:    v_mov_b32_e32 v3, s1
; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT:    s_endpgm
;
; SI-GISEL-LABEL: rsq_f64:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT:    v_rsq_f64_e32 v[0:1], s[2:3]
; SI-GISEL-NEXT:    s_mov_b32 s2, -1
; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-GISEL-NEXT:    s_endpgm
;
; VI-GISEL-LABEL: rsq_f64:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT:    v_rsq_f64_e32 v[0:1], s[2:3]
; VI-GISEL-NEXT:    s_mov_b32 s2, -1
; VI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
; VI-GISEL-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-GISEL-NEXT:    s_endpgm
;
; GFX12-GISEL-LABEL: rsq_f64:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-GISEL-NEXT:    v_mov_b32_e32 v2, 0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    v_rsq_f64_e32 v[0:1], s[2:3]
; GFX12-GISEL-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
; GFX12-GISEL-NEXT:    s_endpgm
  %rsq = call double @llvm.amdgcn.rsq.f64(double %src) #0
  store double %rsq, ptr addrspace(1) %out, align 4
  ret void
}

; TODO: Really these should be constant folded
define amdgpu_kernel void @rsq_f64_constant_4.0(ptr addrspace(1) %out) #1 {
; SI-LABEL: rsq_f64_constant_4.0:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    v_rsq_f64_e32 v[0:1], 4.0
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: rsq_f64_constant_4.0:
; VI:       ; %bb.0:
; VI-NEXT:    v_rsq_f64_e32 v[0:1], 4.0
; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    v_mov_b32_e32 v3, s1
; VI-NEXT:    v_mov_b32_e32 v2, s0
; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT:    s_endpgm
;
; SI-GISEL-LABEL: rsq_f64_constant_4.0:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-GISEL-NEXT:    v_rsq_f64_e32 v[0:1], 4.0
; SI-GISEL-NEXT:    s_mov_b32 s2, -1
; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-GISEL-NEXT:    s_endpgm
;
; VI-GISEL-LABEL: rsq_f64_constant_4.0:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    v_rsq_f64_e32 v[0:1], 4.0
; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-GISEL-NEXT:    s_mov_b32 s2, -1
; VI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-GISEL-NEXT:    s_endpgm
;
; GFX12-GISEL-LABEL: rsq_f64_constant_4.0:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    v_rsq_f64_e32 v[0:1], 4.0
; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-GISEL-NEXT:    v_mov_b32_e32 v2, 0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
; GFX12-GISEL-NEXT:    s_endpgm
  %rsq = call double @llvm.amdgcn.rsq.f64(double 4.0) #0
  store double %rsq, ptr addrspace(1) %out, align 4
  ret void
}

define amdgpu_kernel void @rsq_f64_constant_100.0(ptr addrspace(1) %out) #1 {
; SI-LABEL: rsq_f64_constant_100.0:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    v_rsq_f64_e32 v[0:1], 0x40590000
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: rsq_f64_constant_100.0:
; VI:       ; %bb.0:
; VI-NEXT:    v_rsq_f64_e32 v[0:1], 0x40590000
; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    v_mov_b32_e32 v3, s1
; VI-NEXT:    v_mov_b32_e32 v2, s0
; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT:    s_endpgm
;
; SI-GISEL-LABEL: rsq_f64_constant_100.0:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-GISEL-NEXT:    v_rsq_f64_e32 v[0:1], 0x40590000
; SI-GISEL-NEXT:    s_mov_b32 s2, -1
; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-GISEL-NEXT:    s_endpgm
;
; VI-GISEL-LABEL: rsq_f64_constant_100.0:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    v_rsq_f64_e32 v[0:1], 0x40590000
; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-GISEL-NEXT:    s_mov_b32 s2, -1
; VI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-GISEL-NEXT:    s_endpgm
;
; GFX12-GISEL-LABEL: rsq_f64_constant_100.0:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    v_rsq_f64_e32 v[0:1], 0x40590000
; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-GISEL-NEXT:    v_mov_b32_e32 v2, 0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
; GFX12-GISEL-NEXT:    s_endpgm
  %rsq = call double @llvm.amdgcn.rsq.f64(double 100.0) #0
  store double %rsq, ptr addrspace(1) %out, align 4
  ret void
}

; With SDAG, poison folding happens in target specific combine. With GISel this
; only happens as part of InstCombine so is not tested here.

define amdgpu_kernel void @rsq_undef_f32(ptr addrspace(1) %out) #1 {
; SI-LABEL: rsq_undef_f32:
; SI:       ; %bb.0:
; SI-NEXT:    s_endpgm
;
; VI-LABEL: rsq_undef_f32:
; VI:       ; %bb.0:
; VI-NEXT:    s_endpgm
;
; SI-GISEL-LABEL: rsq_undef_f32:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT:    v_rsq_f32_e32 v0, s0
; SI-GISEL-NEXT:    s_mov_b32 s2, -1
; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT:    s_endpgm
;
; VI-GISEL-LABEL: rsq_undef_f32:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-GISEL-NEXT:    s_mov_b32 s2, -1
; VI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT:    v_rsq_f32_e32 v0, s0
; VI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT:    s_endpgm
;
; GFX12-GISEL-LABEL: rsq_undef_f32:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-GISEL-NEXT:    v_mov_b32_e32 v1, 0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    v_s_rsq_f32 s2, s0
; GFX12-GISEL-NEXT:    s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, s2
; GFX12-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX12-GISEL-NEXT:    s_endpgm
  %rsq = call float @llvm.amdgcn.rsq.f32(float poison)
  store float %rsq, ptr addrspace(1) %out, align 4
  ret void
}

attributes #0 = { nounwind readnone }
attributes #1 = { nounwind }