; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s

define amdgpu_kernel void @test_s_sethalt() {
; GCN-LABEL: test_s_sethalt:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_sethalt 0
; GCN-NEXT:    s_sethalt 1
; GCN-NEXT:    s_sethalt 2
; GCN-NEXT:    s_sethalt 3
; GCN-NEXT:    s_sethalt 4
; GCN-NEXT:    s_sethalt 5
; GCN-NEXT:    s_sethalt 6
; GCN-NEXT:    s_sethalt 7
; GCN-NEXT:    s_endpgm
  call void @llvm.amdgcn.s.sethalt(i32 0)
  call void @llvm.amdgcn.s.sethalt(i32 1)
  call void @llvm.amdgcn.s.sethalt(i32 2)
  call void @llvm.amdgcn.s.sethalt(i32 3)
  call void @llvm.amdgcn.s.sethalt(i32 4)
  call void @llvm.amdgcn.s.sethalt(i32 5)
  call void @llvm.amdgcn.s.sethalt(i32 6)
  call void @llvm.amdgcn.s.sethalt(i32 7)
  ret void
}

define amdgpu_gs void @if_sethalt(i32 %flag) #0 {
; GCN-LABEL: if_sethalt:
; GCN:       ; %bb.0:
; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT:    s_and_saveexec_b64 s[0:1], vcc
; GCN-NEXT:    s_cbranch_execz .LBB1_2
; GCN-NEXT:  ; %bb.1: ; %sethalt
; GCN-NEXT:    s_sethalt 1
; GCN-NEXT:  .LBB1_2: ; %end
; GCN-NEXT:    s_endpgm
  %cond = icmp eq i32 %flag, 0
  br i1 %cond, label %sethalt, label %end

sethalt:
  call void @llvm.amdgcn.s.sethalt(i32 1)
  br label %end

end:
  ret void
}

declare void @llvm.amdgcn.s.sethalt(i32)