; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck %s -check-prefix=GFX12
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck %s -check-prefix=GFX12

define amdgpu_ps void @test_asynccnt() {
; GFX12-LABEL: test_asynccnt:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX12-NEXT:    v_nop
; GFX12-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-NEXT:    s_wait_asynccnt 0x0
; GFX12-NEXT:    s_endpgm
  call void @llvm.amdgcn.s.wait.asynccnt(i16 0)
  ret void
}

define amdgpu_ps void @test_tensorcnt() {
; GFX12-LABEL: test_tensorcnt:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX12-NEXT:    v_nop
; GFX12-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-NEXT:    s_wait_tensorcnt 0x0
; GFX12-NEXT:    s_endpgm
  call void @llvm.amdgcn.s.wait.tensorcnt(i16 0)
  ret void
}

declare void @llvm.amdgcn.s.wait.asynccnt(i16)
declare void @llvm.amdgcn.s.wait.tensorcnt(i16)