; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG-REAL16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG-FAKE16 %s
; xUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-REAL16 %s
; xUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1310 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX13,GFX13-SDAG-REAL16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1310 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX13,GFX13-SDAG-FAKE16 %s
; xUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1310 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX13,GFX13-GISEL-REAL16 %s
; xUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1310 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX13,GFX13-GISEL-FAKE16 %s

; RUN: not llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s
; RUN: not llc -global-isel=1 -global-isel-abort=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s

; ERR: error: <unknown>:0:0: in function tanh_f32 void (ptr addrspace(1), float): intrinsic not supported on subtarget

; FIXME: GlobalISel does not work with bf16

declare float @llvm.amdgcn.tanh.f32(float) #0
declare half @llvm.amdgcn.tanh.f16(half) #0
declare bfloat @llvm.amdgcn.tanh.bf16(bfloat) #0

define amdgpu_kernel void @tanh_f32(ptr addrspace(1) %out, float %src) #1 {
; GFX1250-LABEL: tanh_f32:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0 nv
; GFX1250-NEXT:    v_mov_b32_e32 v1, 0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_tanh_f32_e32 v0, s2
; GFX1250-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-NEXT:    s_endpgm
;
; GFX13-LABEL: tanh_f32:
; GFX13:       ; %bb.0:
; GFX13-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0 nv
; GFX13-NEXT:    v_mov_b32_e32 v1, 0
; GFX13-NEXT:    s_wait_kmcnt 0x0
; GFX13-NEXT:    v_tanh_f32_e32 v0, s2
; GFX13-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX13-NEXT:    s_endpgm
  %tanh = call float @llvm.amdgcn.tanh.f32(float %src) #0
  store float %tanh, ptr addrspace(1) %out, align 4
  ret void
}

; TODO: Really these should be constant folded
define amdgpu_kernel void @tanh_f32_constant_4.0(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: tanh_f32_constant_4.0:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX1250-NEXT:    v_tanh_f32_e32 v0, 4.0
; GFX1250-NEXT:    v_mov_b32_e32 v1, 0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-NEXT:    s_endpgm
;
; GFX13-LABEL: tanh_f32_constant_4.0:
; GFX13:       ; %bb.0:
; GFX13-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX13-NEXT:    v_tanh_f32_e32 v0, 4.0
; GFX13-NEXT:    v_mov_b32_e32 v1, 0
; GFX13-NEXT:    s_wait_kmcnt 0x0
; GFX13-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX13-NEXT:    s_endpgm
  %tanh = call float @llvm.amdgcn.tanh.f32(float 4.0) #0
  store float %tanh, ptr addrspace(1) %out, align 4
  ret void
}

define amdgpu_kernel void @tanh_f32_constant_100.0(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: tanh_f32_constant_100.0:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX1250-NEXT:    v_tanh_f32_e32 v0, 0x42c80000
; GFX1250-NEXT:    v_mov_b32_e32 v1, 0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-NEXT:    s_endpgm
;
; GFX13-LABEL: tanh_f32_constant_100.0:
; GFX13:       ; %bb.0:
; GFX13-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX13-NEXT:    v_tanh_f32_e32 v0, 0x42c80000
; GFX13-NEXT:    v_mov_b32_e32 v1, 0
; GFX13-NEXT:    s_wait_kmcnt 0x0
; GFX13-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX13-NEXT:    s_endpgm
  %tanh = call float @llvm.amdgcn.tanh.f32(float 100.0) #0
  store float %tanh, ptr addrspace(1) %out, align 4
  ret void
}

define amdgpu_kernel void @tanh_undef_f32(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: tanh_undef_f32:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_endpgm
;
; GFX13-LABEL: tanh_undef_f32:
; GFX13:       ; %bb.0:
; GFX13-NEXT:    s_endpgm
  %tanh = call float @llvm.amdgcn.tanh.f32(float undef)
  store float %tanh, ptr addrspace(1) %out, align 4
  ret void
}

define amdgpu_kernel void @tanh_f16(ptr addrspace(1) %out, half %src) #1 {
; GFX1250-SDAG-REAL16-LABEL: tanh_f16:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0 nv
; GFX1250-SDAG-REAL16-NEXT:    v_mov_b32_e32 v1, 0
; GFX1250-SDAG-REAL16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-REAL16-NEXT:    v_tanh_f16_e32 v0.l, s2
; GFX1250-SDAG-REAL16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: tanh_f16:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0 nv
; GFX1250-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    v_tanh_f16_e32 v0, s2
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX13-SDAG-REAL16-LABEL: tanh_f16:
; GFX13-SDAG-REAL16:       ; %bb.0:
; GFX13-SDAG-REAL16-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0 nv
; GFX13-SDAG-REAL16-NEXT:    v_mov_b32_e32 v1, 0
; GFX13-SDAG-REAL16-NEXT:    s_wait_kmcnt 0x0
; GFX13-SDAG-REAL16-NEXT:    v_tanh_f16_e32 v0.l, s2
; GFX13-SDAG-REAL16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX13-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX13-SDAG-FAKE16-LABEL: tanh_f16:
; GFX13-SDAG-FAKE16:       ; %bb.0:
; GFX13-SDAG-FAKE16-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0 nv
; GFX13-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
; GFX13-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX13-SDAG-FAKE16-NEXT:    v_tanh_f16_e32 v0, s2
; GFX13-SDAG-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX13-SDAG-FAKE16-NEXT:    s_endpgm
  %tanh = call half @llvm.amdgcn.tanh.f16(half %src) #0
  store half %tanh, ptr addrspace(1) %out, align 2
  ret void
}

define amdgpu_kernel void @tanh_f16_constant_4.0(ptr addrspace(1) %out) #1 {
; GFX1250-SDAG-REAL16-LABEL: tanh_f16_constant_4.0:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX1250-SDAG-REAL16-NEXT:    v_tanh_f16_e32 v0.l, 4.0
; GFX1250-SDAG-REAL16-NEXT:    v_mov_b32_e32 v1, 0
; GFX1250-SDAG-REAL16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-REAL16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: tanh_f16_constant_4.0:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX1250-SDAG-FAKE16-NEXT:    v_tanh_f16_e32 v0, 4.0
; GFX1250-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX13-SDAG-REAL16-LABEL: tanh_f16_constant_4.0:
; GFX13-SDAG-REAL16:       ; %bb.0:
; GFX13-SDAG-REAL16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX13-SDAG-REAL16-NEXT:    v_tanh_f16_e32 v0.l, 4.0
; GFX13-SDAG-REAL16-NEXT:    v_mov_b32_e32 v1, 0
; GFX13-SDAG-REAL16-NEXT:    s_wait_kmcnt 0x0
; GFX13-SDAG-REAL16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX13-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX13-SDAG-FAKE16-LABEL: tanh_f16_constant_4.0:
; GFX13-SDAG-FAKE16:       ; %bb.0:
; GFX13-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX13-SDAG-FAKE16-NEXT:    v_tanh_f16_e32 v0, 4.0
; GFX13-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
; GFX13-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX13-SDAG-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX13-SDAG-FAKE16-NEXT:    s_endpgm
  %tanh = call half @llvm.amdgcn.tanh.f16(half 4.0) #0
  store half %tanh, ptr addrspace(1) %out, align 2
  ret void
}

define amdgpu_kernel void @tanh_f16_constant_100.0(ptr addrspace(1) %out) #1 {
; GFX1250-SDAG-REAL16-LABEL: tanh_f16_constant_100.0:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX1250-SDAG-REAL16-NEXT:    v_tanh_f16_e32 v0.l, 0x5640
; GFX1250-SDAG-REAL16-NEXT:    v_mov_b32_e32 v1, 0
; GFX1250-SDAG-REAL16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-REAL16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: tanh_f16_constant_100.0:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX1250-SDAG-FAKE16-NEXT:    v_tanh_f16_e32 v0, 0x5640
; GFX1250-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX13-SDAG-REAL16-LABEL: tanh_f16_constant_100.0:
; GFX13-SDAG-REAL16:       ; %bb.0:
; GFX13-SDAG-REAL16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX13-SDAG-REAL16-NEXT:    v_tanh_f16_e32 v0.l, 0x5640
; GFX13-SDAG-REAL16-NEXT:    v_mov_b32_e32 v1, 0
; GFX13-SDAG-REAL16-NEXT:    s_wait_kmcnt 0x0
; GFX13-SDAG-REAL16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX13-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX13-SDAG-FAKE16-LABEL: tanh_f16_constant_100.0:
; GFX13-SDAG-FAKE16:       ; %bb.0:
; GFX13-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX13-SDAG-FAKE16-NEXT:    v_tanh_f16_e32 v0, 0x5640
; GFX13-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
; GFX13-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX13-SDAG-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX13-SDAG-FAKE16-NEXT:    s_endpgm
  %tanh = call half @llvm.amdgcn.tanh.f16(half 100.0) #0
  store half %tanh, ptr addrspace(1) %out, align 2
  ret void
}

define amdgpu_kernel void @tanh_undef_f16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: tanh_undef_f16:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_endpgm
;
; GFX13-LABEL: tanh_undef_f16:
; GFX13:       ; %bb.0:
; GFX13-NEXT:    s_endpgm
  %tanh = call half @llvm.amdgcn.tanh.f16(half undef)
  store half %tanh, ptr addrspace(1) %out, align 2
  ret void
}

define amdgpu_kernel void @tanh_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
; GFX1250-SDAG-REAL16-LABEL: tanh_bf16:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0 nv
; GFX1250-SDAG-REAL16-NEXT:    v_mov_b32_e32 v1, 0
; GFX1250-SDAG-REAL16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-REAL16-NEXT:    v_tanh_bf16_e32 v0.l, s2
; GFX1250-SDAG-REAL16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: tanh_bf16:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0 nv
; GFX1250-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    v_tanh_bf16_e32 v0, s2
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX13-SDAG-REAL16-LABEL: tanh_bf16:
; GFX13-SDAG-REAL16:       ; %bb.0:
; GFX13-SDAG-REAL16-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0 nv
; GFX13-SDAG-REAL16-NEXT:    v_mov_b32_e32 v1, 0
; GFX13-SDAG-REAL16-NEXT:    s_wait_kmcnt 0x0
; GFX13-SDAG-REAL16-NEXT:    v_tanh_bf16_e32 v0.l, s2
; GFX13-SDAG-REAL16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX13-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX13-SDAG-FAKE16-LABEL: tanh_bf16:
; GFX13-SDAG-FAKE16:       ; %bb.0:
; GFX13-SDAG-FAKE16-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0 nv
; GFX13-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
; GFX13-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX13-SDAG-FAKE16-NEXT:    v_tanh_bf16_e32 v0, s2
; GFX13-SDAG-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX13-SDAG-FAKE16-NEXT:    s_endpgm
  %tanh = call bfloat @llvm.amdgcn.tanh.bf16(bfloat %src) #0
  store bfloat %tanh, ptr addrspace(1) %out, align 2
  ret void
}

define amdgpu_kernel void @tanh_bf16_constant_4(ptr addrspace(1) %out) #1 {
; GFX1250-SDAG-REAL16-LABEL: tanh_bf16_constant_4:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX1250-SDAG-REAL16-NEXT:    v_tanh_bf16_e32 v0.l, 4.0
; GFX1250-SDAG-REAL16-NEXT:    v_mov_b32_e32 v1, 0
; GFX1250-SDAG-REAL16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-REAL16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: tanh_bf16_constant_4:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX1250-SDAG-FAKE16-NEXT:    v_tanh_bf16_e32 v0, 4.0
; GFX1250-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX13-SDAG-REAL16-LABEL: tanh_bf16_constant_4:
; GFX13-SDAG-REAL16:       ; %bb.0:
; GFX13-SDAG-REAL16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX13-SDAG-REAL16-NEXT:    v_tanh_bf16_e32 v0.l, 4.0
; GFX13-SDAG-REAL16-NEXT:    v_mov_b32_e32 v1, 0
; GFX13-SDAG-REAL16-NEXT:    s_wait_kmcnt 0x0
; GFX13-SDAG-REAL16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX13-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX13-SDAG-FAKE16-LABEL: tanh_bf16_constant_4:
; GFX13-SDAG-FAKE16:       ; %bb.0:
; GFX13-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX13-SDAG-FAKE16-NEXT:    v_tanh_bf16_e32 v0, 4.0
; GFX13-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
; GFX13-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX13-SDAG-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX13-SDAG-FAKE16-NEXT:    s_endpgm
  %tanh = call bfloat @llvm.amdgcn.tanh.bf16(bfloat 4.0) #0
  store bfloat %tanh, ptr addrspace(1) %out, align 2
  ret void
}

define amdgpu_kernel void @tanh_bf16_constant_100(ptr addrspace(1) %out) #1 {
; GFX1250-SDAG-REAL16-LABEL: tanh_bf16_constant_100:
; GFX1250-SDAG-REAL16:       ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT:    v_nop
; GFX1250-SDAG-REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-REAL16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX1250-SDAG-REAL16-NEXT:    v_tanh_bf16_e32 v0.l, 0x42c8
; GFX1250-SDAG-REAL16-NEXT:    v_mov_b32_e32 v1, 0
; GFX1250-SDAG-REAL16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-REAL16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX1250-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: tanh_bf16_constant_100:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT:    v_nop
; GFX1250-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX1250-SDAG-FAKE16-NEXT:    v_tanh_bf16_e32 v0, 0x42c8
; GFX1250-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX1250-SDAG-FAKE16-NEXT:    s_endpgm
;
; GFX13-SDAG-REAL16-LABEL: tanh_bf16_constant_100:
; GFX13-SDAG-REAL16:       ; %bb.0:
; GFX13-SDAG-REAL16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX13-SDAG-REAL16-NEXT:    v_tanh_bf16_e32 v0.l, 0x42c8
; GFX13-SDAG-REAL16-NEXT:    v_mov_b32_e32 v1, 0
; GFX13-SDAG-REAL16-NEXT:    s_wait_kmcnt 0x0
; GFX13-SDAG-REAL16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX13-SDAG-REAL16-NEXT:    s_endpgm
;
; GFX13-SDAG-FAKE16-LABEL: tanh_bf16_constant_100:
; GFX13-SDAG-FAKE16:       ; %bb.0:
; GFX13-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX13-SDAG-FAKE16-NEXT:    v_tanh_bf16_e32 v0, 0x42c8
; GFX13-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
; GFX13-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX13-SDAG-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX13-SDAG-FAKE16-NEXT:    s_endpgm
  %tanh = call bfloat @llvm.amdgcn.tanh.bf16(bfloat 100.0) #0
  store bfloat %tanh, ptr addrspace(1) %out, align 2
  ret void
}

define amdgpu_kernel void @tanh_undef_bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: tanh_undef_bf16:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_endpgm
;
; GFX13-LABEL: tanh_undef_bf16:
; GFX13:       ; %bb.0:
; GFX13-NEXT:    s_endpgm
  %tanh = call bfloat @llvm.amdgcn.tanh.bf16(bfloat undef)
  store bfloat %tanh, ptr addrspace(1) %out, align 2
  ret void
}

attributes #0 = { nounwind readnone }
attributes #1 = { nounwind }