# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+block-vgpr-csr,+wavefrontsize32,-wavefrontsize64 -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK,W32
# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+block-vgpr-csr,-wavefrontsize32,+wavefrontsize64 -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK,W64

--- |
  define void @one_block() #0 { ret void }
  define void @one_block_csr_only() #0 { ret void }
  define void @multiple_blocks() #0 { ret void }
  define void @reg_tuples() #0 { ret void }
  define void @locals() #0 { ret void }
  define void @other_regs() #0 { ret void }
  define amdgpu_kernel void @entry_func() #0 { ret void }
  define void @multiple_basic_blocks() #0 { ret void }

  attributes #0 = { nounwind }
...

# Block load/store v42 and v45. The mask should be 0x9.

---
name: one_block
tracksRegLiveness: true
machineFunctionInfo:
  stackPtrOffsetReg: $sgpr32
body: |
  bb.0:
    liveins: $sgpr30_sgpr31
    ; W32-LABEL: name: one_block
    ; W32: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73
    ; W32-NEXT: {{  $}}
    ; W32-NEXT: $m0 = S_MOV_B32 9
    ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.0, align 4, addrspace 5)
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec_lo, 32, 0
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec_lo, 32, 96
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr72
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr73
    ; W32-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45
    ; W32-NEXT: $m0 = S_MOV_B32 9
    ; W32-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: ("amdgpu-thread-private" load (s1024) from %stack.0, align 4, addrspace 5)
    ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
    ;
    ; W64-LABEL: name: one_block
    ; W64: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73
    ; W64-NEXT: {{  $}}
    ; W64-NEXT: $m0 = S_MOV_B32 9
    ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.0, align 4, addrspace 5)
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 0
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 192
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr72
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr73
    ; W64-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45
    ; W64-NEXT: $m0 = S_MOV_B32 9
    ; W64-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: ("amdgpu-thread-private" load (s1024) from %stack.0, align 4, addrspace 5)
    ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
    S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45
    S_SETPC_B64_return $sgpr30_sgpr31
...

# Block load/store v40-47 and v56-63 (v48-55 and v64-71 are caller-saved). The
# mask should be 0x00FF00FF.

---
name: one_block_csr_only
tracksRegLiveness: true
machineFunctionInfo:
  stackPtrOffsetReg: $sgpr32
body: |
  bb.0:
    liveins: $sgpr30_sgpr31
    ; W32-LABEL: name: one_block_csr_only
    ; W32: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71
    ; W32-NEXT: {{  $}}
    ; W32-NEXT: $m0 = S_MOV_B32 16711935
    ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.0, align 4, addrspace 5)
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 0
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec_lo, 32, 32
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec_lo, 32, 64
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec_lo, 32, 96
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec_lo, 32, 128
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec_lo, 32, 160
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec_lo, 32, 192
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec_lo, 32, 224
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec_lo, 32, 512
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec_lo, 32, 544
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec_lo, 32, 576
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec_lo, 32, 608
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec_lo, 32, 640
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec_lo, 32, 672
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec_lo, 32, 704
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec_lo, 32, 736
    ; W32-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr42, implicit-def $vgpr43, implicit-def $vgpr44, implicit-def $vgpr45, implicit-def $vgpr46, implicit-def $vgpr47, implicit-def $vgpr48, implicit-def $vgpr49, implicit-def $vgpr50, implicit-def $vgpr51, implicit-def $vgpr52, implicit-def $vgpr53, implicit-def $vgpr54, implicit-def $vgpr55, implicit-def $vgpr56, implicit-def $vgpr57, implicit-def $vgpr58, implicit-def $vgpr59, implicit-def $vgpr60, implicit-def $vgpr61, implicit-def $vgpr62, implicit-def $vgpr63, implicit-def $vgpr64, implicit-def $vgpr65, implicit-def $vgpr66
    ; W32-NEXT: $m0 = S_MOV_B32 16711935
    ; W32-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" load (s1024) from %stack.0, align 4, addrspace 5)
    ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
    ;
    ; W64-LABEL: name: one_block_csr_only
    ; W64: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71
    ; W64-NEXT: {{  $}}
    ; W64-NEXT: $m0 = S_MOV_B32 16711935
    ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.0, align 4, addrspace 5)
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 0
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 64
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 128
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 192
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec, 64, 256
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 320
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec, 64, 384
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec, 64, 448
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec, 64, 1024
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec, 64, 1088
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec, 64, 1152
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec, 64, 1216
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec, 64, 1280
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec, 64, 1344
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec, 64, 1408
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec, 64, 1472
    ; W64-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr42, implicit-def $vgpr43, implicit-def $vgpr44, implicit-def $vgpr45, implicit-def $vgpr46, implicit-def $vgpr47, implicit-def $vgpr48, implicit-def $vgpr49, implicit-def $vgpr50, implicit-def $vgpr51, implicit-def $vgpr52, implicit-def $vgpr53, implicit-def $vgpr54, implicit-def $vgpr55, implicit-def $vgpr56, implicit-def $vgpr57, implicit-def $vgpr58, implicit-def $vgpr59, implicit-def $vgpr60, implicit-def $vgpr61, implicit-def $vgpr62, implicit-def $vgpr63, implicit-def $vgpr64, implicit-def $vgpr65, implicit-def $vgpr66
    ; W64-NEXT: $m0 = S_MOV_B32 16711935
    ; W64-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" load (s1024) from %stack.0, align 4, addrspace 5)
    ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
    S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr42, implicit-def $vgpr43, implicit-def $vgpr44, implicit-def $vgpr45, implicit-def $vgpr46, implicit-def $vgpr47, implicit-def $vgpr48, implicit-def $vgpr49, implicit-def $vgpr50, implicit-def $vgpr51, implicit-def $vgpr52, implicit-def $vgpr53, implicit-def $vgpr54, implicit-def $vgpr55, implicit-def $vgpr56, implicit-def $vgpr57, implicit-def $vgpr58, implicit-def $vgpr59, implicit-def $vgpr60, implicit-def $vgpr61, implicit-def $vgpr62, implicit-def $vgpr63, implicit-def $vgpr64, implicit-def $vgpr65, implicit-def $vgpr66
    S_SETPC_B64_return $sgpr30_sgpr31
...

# Block load/store to/from different blocks.
# Note the mask for storing v232, which is 0x100 because we have to start the
# block at v224 (since the upper limit is 255). For the same reason, the first
# stack slot will be 36 bytes long (the first 32 will be empty, since the memory
# will not get compacted). The second slot, which will hold registers v104 and
# v110, will be 28 bytes long, and finally the third, holding registers v40 and
# v41, will be 8 bytes long.
---
name: multiple_blocks
tracksRegLiveness: true
machineFunctionInfo:
  stackPtrOffsetReg: $sgpr32
body: |
  bb.0:
    liveins: $sgpr30_sgpr31
    ; W32-LABEL: name: multiple_blocks
    ; W32: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263
    ; W32-NEXT: {{  $}}
    ; W32-NEXT: $m0 = S_MOV_B32 3
    ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.0, align 4, addrspace 5)
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 1024
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec_lo, 32, 1056
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr42
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
    ; W32-NEXT: $m0 = S_MOV_B32 65
    ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.1, align 4, addrspace 5)
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr104, 32, $exec_lo, 32, 128
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr105
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr106
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr107
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr108
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr109
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr110, 32, $exec_lo, 32, 320
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr111
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr120
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr121
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr122
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr123
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr124
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr125
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr126
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr127
    ; W32-NEXT: $m0 = S_MOV_B32 1
    ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.2, align 4, addrspace 5)
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr232, 32, $exec_lo, 32, 0
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr233
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr234
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr235
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr236
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr237
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr238
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr239
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr248
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr249
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr250
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr251
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr252
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr253
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr254
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr255
    ; W32-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr104, implicit-def $vgpr110, implicit-def $vgpr232
    ; W32-NEXT: $m0 = S_MOV_B32 1
    ; W32-NEXT: $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr233, implicit $vgpr234, implicit $vgpr235, implicit $vgpr236, implicit $vgpr237, implicit $vgpr238, implicit $vgpr239, implicit $vgpr248, implicit $vgpr249, implicit $vgpr250, implicit $vgpr251, implicit $vgpr252, implicit $vgpr253, implicit $vgpr254, implicit $vgpr255 :: ("amdgpu-thread-private" load (s1024) from %stack.2, align 4, addrspace 5)
    ; W32-NEXT: $m0 = S_MOV_B32 65
    ; W32-NEXT: $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr105, implicit $vgpr106, implicit $vgpr107, implicit $vgpr108, implicit $vgpr109, implicit $vgpr111, implicit $vgpr120, implicit $vgpr121, implicit $vgpr122, implicit $vgpr123, implicit $vgpr124, implicit $vgpr125, implicit $vgpr126, implicit $vgpr127 :: ("amdgpu-thread-private" load (s1024) from %stack.1, align 4, addrspace 5)
    ; W32-NEXT: $m0 = S_MOV_B32 3
    ; W32-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: ("amdgpu-thread-private" load (s1024) from %stack.0, align 4, addrspace 5)
    ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
    ;
    ; W64-LABEL: name: multiple_blocks
    ; W64: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263
    ; W64-NEXT: {{  $}}
    ; W64-NEXT: $m0 = S_MOV_B32 3
    ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.0, align 4, addrspace 5)
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 2048
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 2112
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr42
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
    ; W64-NEXT: $m0 = S_MOV_B32 65
    ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.1, align 4, addrspace 5)
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr104, 32, $exec, 64, 256
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr105
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr106
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr107
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr108
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr109
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr110, 32, $exec, 64, 640
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr111
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr120
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr121
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr122
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr123
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr124
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr125
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr126
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr127
    ; W64-NEXT: $m0 = S_MOV_B32 1
    ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.2, align 4, addrspace 5)
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr232, 32, $exec, 64, 0
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr233
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr234
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr235
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr236
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr237
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr238
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr239
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr248
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr249
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr250
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr251
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr252
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr253
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr254
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr255
    ; W64-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr104, implicit-def $vgpr110, implicit-def $vgpr232
    ; W64-NEXT: $m0 = S_MOV_B32 1
    ; W64-NEXT: $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr233, implicit $vgpr234, implicit $vgpr235, implicit $vgpr236, implicit $vgpr237, implicit $vgpr238, implicit $vgpr239, implicit $vgpr248, implicit $vgpr249, implicit $vgpr250, implicit $vgpr251, implicit $vgpr252, implicit $vgpr253, implicit $vgpr254, implicit $vgpr255 :: ("amdgpu-thread-private" load (s1024) from %stack.2, align 4, addrspace 5)
    ; W64-NEXT: $m0 = S_MOV_B32 65
    ; W64-NEXT: $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr105, implicit $vgpr106, implicit $vgpr107, implicit $vgpr108, implicit $vgpr109, implicit $vgpr111, implicit $vgpr120, implicit $vgpr121, implicit $vgpr122, implicit $vgpr123, implicit $vgpr124, implicit $vgpr125, implicit $vgpr126, implicit $vgpr127 :: ("amdgpu-thread-private" load (s1024) from %stack.1, align 4, addrspace 5)
    ; W64-NEXT: $m0 = S_MOV_B32 3
    ; W64-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: ("amdgpu-thread-private" load (s1024) from %stack.0, align 4, addrspace 5)
    ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
    S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr104, implicit-def $vgpr110, implicit-def $vgpr232
    S_SETPC_B64_return $sgpr30_sgpr31
...

# Make sure we handle register tuples correctly, even when they're straddling
# the boundary between blocks. The first mask should be 0x00000007 (the bottom
# 2 registers from the second tuple are not callee saves), the second
# 0x00000003.

---
name: reg_tuples
tracksRegLiveness: true
machineFunctionInfo:
  stackPtrOffsetReg: $sgpr32
body: |
  bb.0:
    liveins: $sgpr30_sgpr31
    ; W32-LABEL: name: reg_tuples
    ; W32: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103
    ; W32-NEXT: {{  $}}
    ; W32-NEXT: $m0 = S_MOV_B32 7
    ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.0, align 4, addrspace 5)
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 256
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec_lo, 32, 288
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec_lo, 32, 320
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
    ; W32-NEXT: $m0 = S_MOV_B32 3
    ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.1, align 4, addrspace 5)
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr72, 32, $exec_lo, 32, 0
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr73, 32, $exec_lo, 32, 32
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr74
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr75
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr76
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr77
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr78
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr79
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr88
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr89
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr90
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr91
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr92
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr93
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr94
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr95
    ; W32-NEXT: S_NOP 0, implicit-def $vgpr40_vgpr41_vgpr42, implicit-def $vgpr70_vgpr71_vgpr72_vgpr73
    ; W32-NEXT: $m0 = S_MOV_B32 3
    ; W32-NEXT: $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr74, implicit $vgpr75, implicit $vgpr76, implicit $vgpr77, implicit $vgpr78, implicit $vgpr79, implicit $vgpr88, implicit $vgpr89, implicit $vgpr90, implicit $vgpr91, implicit $vgpr92, implicit $vgpr93, implicit $vgpr94, implicit $vgpr95 :: ("amdgpu-thread-private" load (s1024) from %stack.1, align 4, addrspace 5)
    ; W32-NEXT: $m0 = S_MOV_B32 7
    ; W32-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: ("amdgpu-thread-private" load (s1024) from %stack.0, align 4, addrspace 5)
    ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
    ;
    ; W64-LABEL: name: reg_tuples
    ; W64: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103
    ; W64-NEXT: {{  $}}
    ; W64-NEXT: $m0 = S_MOV_B32 7
    ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.0, align 4, addrspace 5)
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 512
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 576
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 640
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
    ; W64-NEXT: $m0 = S_MOV_B32 3
    ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.1, align 4, addrspace 5)
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr72, 32, $exec, 64, 0
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr73, 32, $exec, 64, 64
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr74
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr75
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr76
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr77
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr78
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr79
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr88
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr89
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr90
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr91
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr92
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr93
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr94
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr95
    ; W64-NEXT: S_NOP 0, implicit-def $vgpr40_vgpr41_vgpr42, implicit-def $vgpr70_vgpr71_vgpr72_vgpr73
    ; W64-NEXT: $m0 = S_MOV_B32 3
    ; W64-NEXT: $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr74, implicit $vgpr75, implicit $vgpr76, implicit $vgpr77, implicit $vgpr78, implicit $vgpr79, implicit $vgpr88, implicit $vgpr89, implicit $vgpr90, implicit $vgpr91, implicit $vgpr92, implicit $vgpr93, implicit $vgpr94, implicit $vgpr95 :: ("amdgpu-thread-private" load (s1024) from %stack.1, align 4, addrspace 5)
    ; W64-NEXT: $m0 = S_MOV_B32 7
    ; W64-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: ("amdgpu-thread-private" load (s1024) from %stack.0, align 4, addrspace 5)
    ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
    S_NOP 0, implicit-def $vgpr40_vgpr41_vgpr42, implicit-def $vgpr70_vgpr71_vgpr72_vgpr73
    S_SETPC_B64_return $sgpr30_sgpr31
...

# Make sure we don't overwrite any stack variables.

---
name: locals
tracksRegLiveness: true
machineFunctionInfo:
  stackPtrOffsetReg: $sgpr32
stack:
- { id: 0, type: default, offset: 0, size: 12, alignment: 4,
    stack-id: default, callee-saved-register: '', callee-saved-restored: true,
    local-offset: 0, debug-info-variable: '', debug-info-expression: '',
    debug-info-location: '' }
- { id: 1, type: default, offset: 12, size: 20, alignment: 4,
    stack-id: default, callee-saved-register: '', callee-saved-restored: true,
    local-offset: 0, debug-info-variable: '', debug-info-expression: '',
    debug-info-location: '' }
body: |
  bb.0:
    liveins: $sgpr30_sgpr31, $vgpr48
    ; W32-LABEL: name: locals
    ; W32: liveins: $vgpr48, $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71
    ; W32-NEXT: {{  $}}
    ; W32-NEXT: $m0 = S_MOV_B32 1
    ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.2, align 4, addrspace 5)
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 0
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr41
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr42
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
    ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5)
    ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5)
    ; W32-NEXT: S_NOP 0, implicit-def $vgpr40
    ; W32-NEXT: $m0 = S_MOV_B32 1
    ; W32-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr41, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: ("amdgpu-thread-private" load (s1024) from %stack.2, align 4, addrspace 5)
    ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
    ;
    ; W64-LABEL: name: locals
    ; W64: liveins: $vgpr48, $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71
    ; W64-NEXT: {{  $}}
    ; W64-NEXT: $m0 = S_MOV_B32 1
    ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.2, align 4, addrspace 5)
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 0
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr41
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr42
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
    ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5)
    ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5)
    ; W64-NEXT: S_NOP 0, implicit-def $vgpr40
    ; W64-NEXT: $m0 = S_MOV_B32 1
    ; W64-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr41, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: ("amdgpu-thread-private" load (s1024) from %stack.2, align 4, addrspace 5)
    ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
    SCRATCH_STORE_DWORD_SADDR $vgpr48, %stack.0, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5)
    SCRATCH_STORE_DWORD_SADDR $vgpr48, %stack.1, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5)
    S_NOP 0, implicit-def $vgpr40
    S_SETPC_B64_return $sgpr30_sgpr31
...

# Make sure we don't break SGPR or WWM handling, and also that we don't
# block-spill WWM VGPRs that have already been spilled (the mask for the block
# load/store should be 0x9 because we don't want to include v41 or v42).
# Use all VGPRs up to v40, so the WWM registers v41 and v42 and the VGPR used
# for SGPR spills remain within the block.

---
name: other_regs
tracksRegLiveness: true
machineFunctionInfo:
  stackPtrOffsetReg: $sgpr32
  wwmReservedRegs:
    - '$vgpr41'
    - '$vgpr42'
body: |
  bb.0:
    liveins: $sgpr30_sgpr31, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40
    ; W32-LABEL: name: other_regs
    ; W32: liveins: $sgpr48, $sgpr30_sgpr31, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71
    ; W32-NEXT: {{  $}}
    ; W32-NEXT: $sgpr0 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
    ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr41, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5)
    ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr42, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5)
    ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr44, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5)
    ; W32-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0
    ; W32-NEXT: $m0 = S_MOV_B32 9
    ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.4, align 4, addrspace 5)
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 0
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr41
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr42
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec_lo, 32, 96
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
    ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
    ; W32-NEXT: $vgpr44 = SI_SPILL_S32_TO_VGPR $sgpr48, 0, $vgpr44
    ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr48, $vgpr44, 0, 32
    ; W32-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr43, implicit-def $sgpr22, implicit-def $sgpr48, implicit-def $m0, implicit-def $exec
    ; W32-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, implicit $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40
    ; W32-NEXT: $sgpr48 = SI_RESTORE_S32_FROM_VGPR $vgpr44, 0
    ; W32-NEXT: $m0 = S_MOV_B32 9
    ; W32-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr41, implicit $vgpr42, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: ("amdgpu-thread-private" load (s1024) from %stack.4, align 4, addrspace 5)
    ; W32-NEXT: $sgpr0 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
    ; W32-NEXT: $vgpr41 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5)
    ; W32-NEXT: $vgpr42 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5)
    ; W32-NEXT: $vgpr44 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5)
    ; W32-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0
    ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
    ;
    ; W64-LABEL: name: other_regs
    ; W64: liveins: $sgpr48, $sgpr30_sgpr31, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71
    ; W64-NEXT: {{  $}}
    ; W64-NEXT: $sgpr0_sgpr1 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
    ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr41, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5)
    ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr42, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5)
    ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr44, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5)
    ; W64-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1
    ; W64-NEXT: $m0 = S_MOV_B32 9
    ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.4, align 4, addrspace 5)
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 0
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr41
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr42
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 192
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
    ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
    ; W64-NEXT: $vgpr44 = SI_SPILL_S32_TO_VGPR $sgpr48, 0, $vgpr44
    ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr48, $vgpr44, 0, 32
    ; W64-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr43, implicit-def $sgpr22, implicit-def $sgpr48, implicit-def $m0, implicit-def $exec
    ; W64-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, implicit $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40
    ; W64-NEXT: $sgpr48 = SI_RESTORE_S32_FROM_VGPR $vgpr44, 0
    ; W64-NEXT: $m0 = S_MOV_B32 9
    ; W64-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr41, implicit $vgpr42, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: ("amdgpu-thread-private" load (s1024) from %stack.4, align 4, addrspace 5)
    ; W64-NEXT: $sgpr0_sgpr1 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
    ; W64-NEXT: $vgpr41 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5)
    ; W64-NEXT: $vgpr42 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5)
    ; W64-NEXT: $vgpr44 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5)
    ; W64-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1
    ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
    S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr43, implicit-def $sgpr22, implicit-def $sgpr48, implicit-def $m0, implicit-def $exec
    S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, implicit $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40

    S_SETPC_B64_return $sgpr30_sgpr31
...

# Make sure we don't break anything for entry functions.

---
name: entry_func
tracksRegLiveness: true
machineFunctionInfo:
  stackPtrOffsetReg: $sgpr32
body: |
  bb.0:
    liveins: $sgpr30_sgpr31
    ; CHECK-LABEL: name: entry_func
    ; CHECK: liveins: $sgpr30_sgpr31
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45, implicit-def $vgpr51
    ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
    S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45, implicit-def $vgpr51
    S_SETPC_B64_return $sgpr30_sgpr31
...

---
name: multiple_basic_blocks
tracksRegLiveness: true
machineFunctionInfo:
  stackPtrOffsetReg: $sgpr32
body: |
  ; W32-LABEL: name: multiple_basic_blocks
  ; W32: bb.0:
  ; W32-NEXT:   successors: %bb.1(0x80000000)
  ; W32-NEXT:   liveins: $vgpr44, $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73
  ; W32-NEXT: {{  $}}
  ; W32-NEXT:   $m0 = S_MOV_B32 11
  ; W32-NEXT:   SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.0, align 4, addrspace 5)
  ; W32-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec_lo, 32, 0
  ; W32-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec_lo, 32, 32
  ; W32-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr44
  ; W32-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec_lo, 32, 96
  ; W32-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr46
  ; W32-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr47
  ; W32-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr56
  ; W32-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr57
  ; W32-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr58
  ; W32-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr59
  ; W32-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr60
  ; W32-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr61
  ; W32-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr62
  ; W32-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr63
  ; W32-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr72
  ; W32-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr73
  ; W32-NEXT:   S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45
  ; W32-NEXT:   S_BRANCH %bb.1
  ; W32-NEXT: {{  $}}
  ; W32-NEXT: bb.1:
  ; W32-NEXT:   successors: %bb.2(0x80000000)
  ; W32-NEXT:   liveins: $vgpr44, $sgpr30_sgpr31
  ; W32-NEXT: {{  $}}
  ; W32-NEXT:   S_NOP 0, implicit-def $vgpr43, implicit $vgpr44
  ; W32-NEXT:   S_BRANCH %bb.2
  ; W32-NEXT: {{  $}}
  ; W32-NEXT: bb.2:
  ; W32-NEXT:   liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73
  ; W32-NEXT: {{  $}}
  ; W32-NEXT:   $m0 = S_MOV_B32 11
  ; W32-NEXT:   $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: ("amdgpu-thread-private" load (s1024) from %stack.0, align 4, addrspace 5)
  ; W32-NEXT:   S_SETPC_B64_return $sgpr30_sgpr31
  ;
  ; W64-LABEL: name: multiple_basic_blocks
  ; W64: bb.0:
  ; W64-NEXT:   successors: %bb.1(0x80000000)
  ; W64-NEXT:   liveins: $vgpr44, $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73
  ; W64-NEXT: {{  $}}
  ; W64-NEXT:   $m0 = S_MOV_B32 11
  ; W64-NEXT:   SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.0, align 4, addrspace 5)
  ; W64-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 0
  ; W64-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 64
  ; W64-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr44
  ; W64-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 192
  ; W64-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr46
  ; W64-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr47
  ; W64-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr56
  ; W64-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr57
  ; W64-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr58
  ; W64-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr59
  ; W64-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr60
  ; W64-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr61
  ; W64-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr62
  ; W64-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr63
  ; W64-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr72
  ; W64-NEXT:   frame-setup CFI_INSTRUCTION same_value $vgpr73
  ; W64-NEXT:   S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45
  ; W64-NEXT:   S_BRANCH %bb.1
  ; W64-NEXT: {{  $}}
  ; W64-NEXT: bb.1:
  ; W64-NEXT:   successors: %bb.2(0x80000000)
  ; W64-NEXT:   liveins: $vgpr44, $sgpr30_sgpr31
  ; W64-NEXT: {{  $}}
  ; W64-NEXT:   S_NOP 0, implicit-def $vgpr43, implicit $vgpr44
  ; W64-NEXT:   S_BRANCH %bb.2
  ; W64-NEXT: {{  $}}
  ; W64-NEXT: bb.2:
  ; W64-NEXT:   liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73
  ; W64-NEXT: {{  $}}
  ; W64-NEXT:   $m0 = S_MOV_B32 11
  ; W64-NEXT:   $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: ("amdgpu-thread-private" load (s1024) from %stack.0, align 4, addrspace 5)
  ; W64-NEXT:   S_SETPC_B64_return $sgpr30_sgpr31
  bb.0:
    liveins: $sgpr30_sgpr31, $vgpr44
    S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45
    S_BRANCH %bb.1

  bb.1:
    liveins: $sgpr30_sgpr31, $vgpr44
    S_NOP 0, implicit-def $vgpr43, implicit $vgpr44
    S_BRANCH %bb.2

  bb.2:
    liveins: $sgpr30_sgpr31
    S_SETPC_B64_return $sgpr30_sgpr31
...