# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -run-pass=greedy,amdgpu-rewrite-agpr-copy-mfma -verify-machineinstrs -o - %s | FileCheck %s
# CHECK: bb.1:
# CHECK: dead %{{[0-9]+}}:vreg_128_align2 = V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, 4, 4, %{{[0-9]+}}, %[[REG:[0-9]+]], 4, 0, implicit $mode, implicit $exec
# CHECK: %{{[0-9]+}}:agpr_32 = IMPLICIT_DEF
# CHECK: %[[REG]]:vgpr_32 = COPY %{{[0-9]+}}

# Test for issue in amdgpu-rewrite-agpr-copy-mfma, which reassigns scale operand
# in vgpr_32 register to agpr_32, not permitted by instruction format.
---
name:            test
tracksRegLiveness: true
body:             |
  bb.0:
    liveins:
 
    %0:vgpr_32 = IMPLICIT_DEF
    %1:av_128_align2 = IMPLICIT_DEF
    undef %2.sub0:vreg_128_align2 = IMPLICIT_DEF
 
  bb.1:
    liveins:
 
    %3:vgpr_32 = IMPLICIT_DEF
    %4:av_128_align2 = IMPLICIT_DEF
    %5:vreg_128_align2 = V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 %4, %1, %2, 4, 4, %3, %0, 4, 0, implicit $mode, implicit $exec
    %6:agpr_32 = IMPLICIT_DEF
    %0:vgpr_32 = COPY %6
    S_CBRANCH_SCC1 %bb.1, implicit undef $scc
    S_BRANCH %bb.2
 
  bb.2:
    liveins:
 
    S_ENDPGM 0
...