# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck %s

---
name:            constrain_readfirstlane_av
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: constrain_readfirstlane_av
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $vgpr0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY]], implicit $exec
  ; CHECK-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_READFIRSTLANE_B32_]], [[DEF]], implicit-def dead $scc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[S_MUL_I32_:%[0-9]+]]:sreg_32 = S_MUL_I32 [[S_AND_B32_]], [[S_AND_B32_]]
  ; CHECK-NEXT:   [[S_MUL_HI_U32_:%[0-9]+]]:sreg_32 = S_MUL_HI_U32 [[S_AND_B32_]], [[S_MUL_I32_]]
  ; CHECK-NEXT:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_MUL_HI_U32_]], [[S_MUL_I32_]], implicit-def dead $scc
  ; CHECK-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
  ; CHECK-NEXT:   S_BRANCH %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    liveins: $vgpr0

    %0:sreg_32 = IMPLICIT_DEF
    %1:av_32 = COPY $vgpr0
    %2:sreg_32 = COPY %1
    %3:sreg_32 = S_AND_B32 %2, %0, implicit-def dead $scc

  bb.1:
    %4:sreg_32 = S_MUL_I32 %3, %3
    %5:sreg_32 = S_MUL_HI_U32 %3, %4
    %6:sreg_32 = S_ADD_I32 %5, %4, implicit-def dead $scc
    S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
    S_BRANCH %bb.2

  bb.2:
    S_ENDPGM 0
...

# Need to respect subregister on copy source
---
name:            constrain_readfirstlane_av64
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: constrain_readfirstlane_av64
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $vgpr0_vgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
  ; CHECK-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY]].sub0, implicit $exec
  ; CHECK-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_READFIRSTLANE_B32_]], [[DEF]], implicit-def dead $scc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[S_MUL_I32_:%[0-9]+]]:sreg_32 = S_MUL_I32 [[S_AND_B32_]], [[S_AND_B32_]]
  ; CHECK-NEXT:   [[S_MUL_HI_U32_:%[0-9]+]]:sreg_32 = S_MUL_HI_U32 [[S_AND_B32_]], [[S_MUL_I32_]]
  ; CHECK-NEXT:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_MUL_HI_U32_]], [[S_MUL_I32_]], implicit-def dead $scc
  ; CHECK-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
  ; CHECK-NEXT:   S_BRANCH %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    liveins: $vgpr0_vgpr1

    %0:sreg_32 = IMPLICIT_DEF
    %1:av_64 = COPY $vgpr0_vgpr1
    %2:sreg_32 = COPY %1.sub0
    %3:sreg_32 = S_AND_B32 %2, %0, implicit-def dead $scc

  bb.1:
    %4:sreg_32 = S_MUL_I32 %3, %3
    %5:sreg_32 = S_MUL_HI_U32 %3, %4
    %6:sreg_32 = S_ADD_I32 %5, %4, implicit-def dead $scc
    S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
    S_BRANCH %bb.2

  bb.2:
    S_ENDPGM 0
...

---
name:            constrain_readfirstlane_av64_subreg_m0
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: constrain_readfirstlane_av64_subreg_m0
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY]].sub0, implicit $exec
    ; CHECK-NEXT: $m0 = COPY [[V_READFIRSTLANE_B32_]]
    %0:sreg_32 = IMPLICIT_DEF
    %1:av_64 = COPY $vgpr0_vgpr1
    $m0 = COPY %1.sub0
...