; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple=amdgcn -mcpu=gfx908 < %s | FileCheck -check-prefixes=GCN,GFX908 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -amdgpu-mfma-vgpr-form=0 < %s | FileCheck -check-prefixes=GCN,GFX90A %s define amdgpu_kernel void @max_12regs_13a_used(i32 %cond, ptr addrspace(1) %arg, ptr addrspace(1) %out) #2 { ; GFX908-LABEL: max_12regs_13a_used: ; GFX908: ; %bb.0: ; %bb ; GFX908-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c ; GFX908-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX908-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX908-NEXT: s_waitcnt lgkmcnt(0) ; GFX908-NEXT: s_cmp_lg_u32 s0, 0 ; GFX908-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX908-NEXT: s_waitcnt lgkmcnt(0) ; GFX908-NEXT: v_mov_b32_e32 v5, s8 ; GFX908-NEXT: v_mov_b32_e32 v1, s9 ; GFX908-NEXT: v_mov_b32_e32 v2, s10 ; GFX908-NEXT: v_accvgpr_write_b32 a0, v5 ; GFX908-NEXT: v_mov_b32_e32 v5, s11 ; GFX908-NEXT: v_accvgpr_write_b32 a1, v1 ; GFX908-NEXT: v_accvgpr_write_b32 a2, v2 ; GFX908-NEXT: v_accvgpr_write_b32 a3, v5 ; GFX908-NEXT: s_nop 0 ; GFX908-NEXT: v_mfma_f32_4x4x1f32 a[0:3], v0, v0, a[0:3] ; GFX908-NEXT: v_mfma_f32_4x4x1f32 a[4:7], v0, v0, a[0:3] ; GFX908-NEXT: s_cbranch_scc0 .LBB0_2 ; GFX908-NEXT: ; %bb.1: ; %st ; GFX908-NEXT: ;;#ASMSTART ; GFX908-NEXT: ;;#ASMEND ; GFX908-NEXT: s_endpgm ; GFX908-NEXT: .LBB0_2: ; %use ; GFX908-NEXT: s_nop 2 ; GFX908-NEXT: v_accvgpr_read_b32 v1, a4 ; GFX908-NEXT: v_accvgpr_read_b32 v4, a7 ; GFX908-NEXT: v_accvgpr_read_b32 v2, a5 ; GFX908-NEXT: v_accvgpr_read_b32 v3, a6 ; GFX908-NEXT: v_accvgpr_write_b32 a4, 4 ; GFX908-NEXT: v_accvgpr_write_b32 a8, 5 ; GFX908-NEXT: v_accvgpr_write_b32 a9, 1 ; GFX908-NEXT: v_accvgpr_write_b32 a10, 2 ; GFX908-NEXT: v_accvgpr_write_b32 a11, 3 ; GFX908-NEXT: ;;#ASMSTART ; GFX908-NEXT: ;;#ASMEND ; GFX908-NEXT: v_accvgpr_write_b32 a7, v4 ; GFX908-NEXT: v_accvgpr_write_b32 a6, v3 ; GFX908-NEXT: v_accvgpr_write_b32 a5, v2 ; GFX908-NEXT: v_accvgpr_write_b32 a4, v1 ; GFX908-NEXT: v_mov_b32_e32 v1, v0 ; GFX908-NEXT: v_mov_b32_e32 v2, v0 ; GFX908-NEXT: v_mov_b32_e32 v3, v0 ; GFX908-NEXT: v_mov_b32_e32 v4, 0 ; GFX908-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7] ; GFX908-NEXT: s_waitcnt vmcnt(0) ; GFX908-NEXT: ;;#ASMSTART ; GFX908-NEXT: ;;#ASMEND ; GFX908-NEXT: s_endpgm ; ; GFX90A-LABEL: max_12regs_13a_used: ; GFX90A: ; %bb.0: ; %bb ; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c ; GFX90A-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX90A-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_cmp_lg_u32 s0, 0 ; GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: v_accvgpr_write_b32 a0, s8 ; GFX90A-NEXT: v_accvgpr_write_b32 a1, s9 ; GFX90A-NEXT: v_accvgpr_write_b32 a2, s10 ; GFX90A-NEXT: v_accvgpr_write_b32 a3, s11 ; GFX90A-NEXT: s_nop 1 ; GFX90A-NEXT: v_mfma_f32_4x4x1f32 a[0:3], v0, v0, a[0:3] ; GFX90A-NEXT: v_mfma_f32_4x4x1f32 a[4:7], v0, v0, a[0:3] ; GFX90A-NEXT: s_cbranch_scc0 .LBB0_2 ; GFX90A-NEXT: ; %bb.1: ; %st ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_endpgm ; GFX90A-NEXT: .LBB0_2: ; %use ; GFX90A-NEXT: s_nop 3 ; GFX90A-NEXT: v_accvgpr_read_b32 v9, a7 ; GFX90A-NEXT: v_accvgpr_read_b32 v8, a6 ; GFX90A-NEXT: v_accvgpr_read_b32 v7, a5 ; GFX90A-NEXT: v_accvgpr_read_b32 v6, a4 ; GFX90A-NEXT: v_accvgpr_write_b32 a4, 4 ; GFX90A-NEXT: v_accvgpr_write_b32 a8, 5 ; GFX90A-NEXT: v_accvgpr_write_b32 a9, 1 ; GFX90A-NEXT: v_accvgpr_write_b32 a10, 2 ; GFX90A-NEXT: v_accvgpr_write_b32 a11, 3 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_accvgpr_write_b32 a4, v6 ; GFX90A-NEXT: v_mov_b32_e32 v4, 0 ; GFX90A-NEXT: v_accvgpr_write_b32 a5, v7 ; GFX90A-NEXT: v_accvgpr_write_b32 a6, v8 ; GFX90A-NEXT: v_accvgpr_write_b32 a7, v9 ; GFX90A-NEXT: v_mov_b32_e32 v1, v0 ; GFX90A-NEXT: v_mov_b32_e32 v2, v0 ; GFX90A-NEXT: v_mov_b32_e32 v3, v0 ; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7] ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_endpgm bb: %in.1 = load <4 x float>, ptr addrspace(1) %arg %mai.1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 1.0, <4 x float> %in.1, i32 0, i32 0, i32 0) %mai.2 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 1.0, <4 x float> %mai.1, i32 0, i32 0, i32 0) %cmp = icmp eq i32 %cond, 0 br i1 %cmp, label %use, label %st use: call void asm sideeffect "", "a,a,a,a,a"(i32 1, i32 2, i32 3, i32 4, i32 5) store volatile <4 x float> , ptr addrspace(1) %out br label %st st: %gep1 = getelementptr <4 x float>, ptr addrspace(1) %out, i64 16 %gep2 = getelementptr <4 x float>, ptr addrspace(1) %out, i64 32 call void asm sideeffect "", "a,a"(<4 x float> %mai.1, <4 x float> %mai.2) ret void } ; GCN: ScratchSize: 0 define amdgpu_kernel void @max_10_vgprs_used_9a() #1 { ; GFX908-LABEL: max_10_vgprs_used_9a: ; GFX908: ; %bb.0: ; GFX908-NEXT: ;;#ASMSTART ; GFX908-NEXT: ;;#ASMEND ; GFX908-NEXT: v_accvgpr_read_b32 v0, a0 ; GFX908-NEXT: v_accvgpr_read_b32 v3, a3 ; GFX908-NEXT: v_accvgpr_read_b32 v1, a1 ; GFX908-NEXT: v_accvgpr_read_b32 v2, a2 ; GFX908-NEXT: ;;#ASMSTART ; GFX908-NEXT: ;;#ASMEND ; GFX908-NEXT: ;;#ASMSTART ; GFX908-NEXT: ;;#ASMEND ; GFX908-NEXT: ;;#ASMSTART ; GFX908-NEXT: ;;#ASMEND ; GFX908-NEXT: v_accvgpr_read_b32 v5, a2 ; GFX908-NEXT: v_accvgpr_read_b32 v4, a1 ; GFX908-NEXT: v_accvgpr_write_b32 a4, v3 ; GFX908-NEXT: v_accvgpr_write_b32 a1, v0 ; GFX908-NEXT: v_accvgpr_write_b32 a3, v2 ; GFX908-NEXT: v_accvgpr_write_b32 a2, v1 ; GFX908-NEXT: ;;#ASMSTART ; GFX908-NEXT: ;;#ASMEND ; GFX908-NEXT: v_accvgpr_write_b32 a0, v4 ; GFX908-NEXT: v_accvgpr_write_b32 a1, v5 ; GFX908-NEXT: ;;#ASMSTART ; GFX908-NEXT: ;;#ASMEND ; GFX908-NEXT: s_endpgm ; ; GFX90A-LABEL: max_10_vgprs_used_9a: ; GFX90A: ; %bb.0: ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0 ; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1 ; GFX90A-NEXT: v_accvgpr_read_b32 v2, a2 ; GFX90A-NEXT: v_accvgpr_read_b32 v3, a3 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_accvgpr_read_b32 v5, a3 ; GFX90A-NEXT: v_accvgpr_read_b32 v4, a2 ; GFX90A-NEXT: v_accvgpr_write_b32 a5, v3 ; GFX90A-NEXT: v_accvgpr_write_b32 a4, v2 ; GFX90A-NEXT: v_accvgpr_write_b32 a3, v1 ; GFX90A-NEXT: v_accvgpr_write_b32 a2, v0 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_accvgpr_write_b32 a0, v4 ; GFX90A-NEXT: v_accvgpr_write_b32 a1, v5 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_endpgm %a1 = call <4 x i32> asm sideeffect "", "=a"() %a2 = call <4 x i32> asm sideeffect "", "=a"() %a3 = call i32 asm sideeffect "", "=a"() %a4 = call <2 x i32> asm sideeffect "", "=a"() call void asm sideeffect "", "a,a,a"(<4 x i32> %a1, <4 x i32> %a2, i32 %a3) call void asm sideeffect "", "a"(<2 x i32> %a4) ret void } ; GCN: ScratchSize: 0 define amdgpu_kernel void @max_32regs_mfma32(ptr addrspace(1) %arg) #3 { ; GFX908-LABEL: max_32regs_mfma32: ; GFX908: ; %bb.0: ; %bb ; GFX908-NEXT: v_mov_b32_e32 v1, 0x40400000 ; GFX908-NEXT: v_mov_b32_e32 v2, 0x40c00000 ; GFX908-NEXT: v_mov_b32_e32 v3, 0x40e00000 ; GFX908-NEXT: v_accvgpr_write_b32 a2, v1 ; GFX908-NEXT: v_mov_b32_e32 v1, 0x40a00000 ; GFX908-NEXT: v_accvgpr_write_b32 a5, v2 ; GFX908-NEXT: v_accvgpr_write_b32 a6, v3 ; GFX908-NEXT: v_accvgpr_write_b32 a4, v1 ; GFX908-NEXT: v_mov_b32_e32 v1, 0x41000000 ; GFX908-NEXT: v_mov_b32_e32 v2, 0x41100000 ; GFX908-NEXT: v_mov_b32_e32 v3, 0x41200000 ; GFX908-NEXT: v_accvgpr_write_b32 a7, v1 ; GFX908-NEXT: v_accvgpr_write_b32 a8, v2 ; GFX908-NEXT: v_accvgpr_write_b32 a9, v3 ; GFX908-NEXT: v_mov_b32_e32 v1, 0x41300000 ; GFX908-NEXT: v_mov_b32_e32 v2, 0x41400000 ; GFX908-NEXT: v_mov_b32_e32 v3, 0x41500000 ; GFX908-NEXT: v_accvgpr_write_b32 a10, v1 ; GFX908-NEXT: v_accvgpr_write_b32 a11, v2 ; GFX908-NEXT: v_accvgpr_write_b32 a12, v3 ; GFX908-NEXT: v_mov_b32_e32 v1, 0x41600000 ; GFX908-NEXT: v_mov_b32_e32 v2, 0x41700000 ; GFX908-NEXT: v_mov_b32_e32 v3, 0x41800000 ; GFX908-NEXT: v_accvgpr_write_b32 a13, v1 ; GFX908-NEXT: v_accvgpr_write_b32 a14, v2 ; GFX908-NEXT: v_accvgpr_write_b32 a15, v3 ; GFX908-NEXT: v_mov_b32_e32 v1, 0x41880000 ; GFX908-NEXT: v_mov_b32_e32 v2, 0x41900000 ; GFX908-NEXT: v_mov_b32_e32 v3, 0x41980000 ; GFX908-NEXT: v_accvgpr_write_b32 a16, v1 ; GFX908-NEXT: v_accvgpr_write_b32 a17, v2 ; GFX908-NEXT: v_accvgpr_write_b32 a18, v3 ; GFX908-NEXT: v_mov_b32_e32 v1, 0x41a00000 ; GFX908-NEXT: v_mov_b32_e32 v2, 0x41a80000 ; GFX908-NEXT: v_mov_b32_e32 v3, 0x41b00000 ; GFX908-NEXT: v_accvgpr_write_b32 a19, v1 ; GFX908-NEXT: v_accvgpr_write_b32 a20, v2 ; GFX908-NEXT: v_accvgpr_write_b32 a21, v3 ; GFX908-NEXT: v_mov_b32_e32 v1, 0x41b80000 ; GFX908-NEXT: v_mov_b32_e32 v2, 0x41c00000 ; GFX908-NEXT: v_mov_b32_e32 v3, 0x41c80000 ; GFX908-NEXT: v_accvgpr_write_b32 a22, v1 ; GFX908-NEXT: v_accvgpr_write_b32 a23, v2 ; GFX908-NEXT: v_accvgpr_write_b32 a24, v3 ; GFX908-NEXT: v_mov_b32_e32 v1, 0x41d00000 ; GFX908-NEXT: v_mov_b32_e32 v2, 0x41d80000 ; GFX908-NEXT: v_mov_b32_e32 v3, 0x41e00000 ; GFX908-NEXT: v_accvgpr_write_b32 a25, v1 ; GFX908-NEXT: v_accvgpr_write_b32 a26, v2 ; GFX908-NEXT: v_accvgpr_write_b32 a27, v3 ; GFX908-NEXT: v_mov_b32_e32 v1, 0x41e80000 ; GFX908-NEXT: v_mov_b32_e32 v2, 0x41f00000 ; GFX908-NEXT: v_mov_b32_e32 v3, 0x41f80000 ; GFX908-NEXT: v_mov_b32_e32 v4, 1.0 ; GFX908-NEXT: ;;#ASMSTART ; GFX908-NEXT: ;;#ASMEND ; GFX908-NEXT: v_accvgpr_read_b32 v5, a0 ; GFX908-NEXT: v_accvgpr_write_b32 a0, 1.0 ; GFX908-NEXT: v_accvgpr_write_b32 a1, 2.0 ; GFX908-NEXT: v_accvgpr_write_b32 a3, 4.0 ; GFX908-NEXT: v_accvgpr_write_b32 a28, v1 ; GFX908-NEXT: v_accvgpr_write_b32 a29, v2 ; GFX908-NEXT: v_accvgpr_write_b32 a30, v3 ; GFX908-NEXT: v_accvgpr_write_b32 a31, 2.0 ; GFX908-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX908-NEXT: v_mfma_f32_32x32x1f32 a[0:31], v4, v4, a[0:31] ; GFX908-NEXT: v_mov_b32_e32 v0, 0 ; GFX908-NEXT: s_nop 13 ; GFX908-NEXT: v_accvgpr_write_b32 a1, v5 ; GFX908-NEXT: ;;#ASMSTART ; GFX908-NEXT: ;;#ASMEND ; GFX908-NEXT: s_nop 1 ; GFX908-NEXT: v_accvgpr_read_b32 v1, a0 ; GFX908-NEXT: s_waitcnt lgkmcnt(0) ; GFX908-NEXT: s_nop 0 ; GFX908-NEXT: global_store_dword v0, v1, s[2:3] ; GFX908-NEXT: s_endpgm ; ; GFX90A-LABEL: max_32regs_mfma32: ; GFX90A: ; %bb.0: ; %bb ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x40400000 ; GFX90A-NEXT: v_accvgpr_write_b32 a2, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x40a00000 ; GFX90A-NEXT: v_accvgpr_write_b32 a4, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x40c00000 ; GFX90A-NEXT: v_accvgpr_write_b32 a5, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x40e00000 ; GFX90A-NEXT: v_accvgpr_write_b32 a6, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41000000 ; GFX90A-NEXT: v_accvgpr_write_b32 a7, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41100000 ; GFX90A-NEXT: v_accvgpr_write_b32 a8, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41200000 ; GFX90A-NEXT: v_accvgpr_write_b32 a9, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41300000 ; GFX90A-NEXT: v_accvgpr_write_b32 a10, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41400000 ; GFX90A-NEXT: v_accvgpr_write_b32 a11, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41500000 ; GFX90A-NEXT: v_accvgpr_write_b32 a12, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41600000 ; GFX90A-NEXT: v_accvgpr_write_b32 a13, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41700000 ; GFX90A-NEXT: v_accvgpr_write_b32 a14, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41800000 ; GFX90A-NEXT: v_accvgpr_write_b32 a15, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41880000 ; GFX90A-NEXT: v_accvgpr_write_b32 a16, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41900000 ; GFX90A-NEXT: v_accvgpr_write_b32 a17, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41980000 ; GFX90A-NEXT: v_accvgpr_write_b32 a18, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41a00000 ; GFX90A-NEXT: v_accvgpr_write_b32 a19, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41a80000 ; GFX90A-NEXT: v_accvgpr_write_b32 a20, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41b00000 ; GFX90A-NEXT: v_accvgpr_write_b32 a21, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41b80000 ; GFX90A-NEXT: v_accvgpr_write_b32 a22, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41c00000 ; GFX90A-NEXT: v_accvgpr_write_b32 a23, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41c80000 ; GFX90A-NEXT: v_accvgpr_write_b32 a24, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41d00000 ; GFX90A-NEXT: v_accvgpr_write_b32 a25, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41d80000 ; GFX90A-NEXT: v_accvgpr_write_b32 a26, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41e00000 ; GFX90A-NEXT: v_mov_b32_e32 v2, 1.0 ; GFX90A-NEXT: v_accvgpr_write_b32 a27, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41e80000 ; GFX90A-NEXT: v_accvgpr_write_b32 a28, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41f00000 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_accvgpr_write_b32 a1, 2.0 ; GFX90A-NEXT: v_accvgpr_write_b32 a29, v1 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x41f80000 ; GFX90A-NEXT: v_accvgpr_read_b32 v3, a0 ; GFX90A-NEXT: v_accvgpr_write_b32 a0, 1.0 ; GFX90A-NEXT: v_accvgpr_write_b32 a3, 4.0 ; GFX90A-NEXT: v_accvgpr_write_b32 a30, v1 ; GFX90A-NEXT: v_accvgpr_mov_b32 a31, a1 ; GFX90A-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX90A-NEXT: v_mov_b32_e32 v0, 0 ; GFX90A-NEXT: v_mfma_f32_32x32x1f32 a[0:31], v2, v2, a[0:31] ; GFX90A-NEXT: s_nop 15 ; GFX90A-NEXT: s_nop 2 ; GFX90A-NEXT: v_accvgpr_write_b32 a1, v3 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: global_store_dword v0, a0, s[2:3] ; GFX90A-NEXT: s_endpgm bb: %v = call i32 asm sideeffect "", "=a"() br label %use use: %mai.1 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.0, float 1.0, <32 x float> , i32 0, i32 0, i32 0) call void asm sideeffect "", "a"(i32 %v) %elt1 = extractelement <32 x float> %mai.1, i32 0 store float %elt1, ptr addrspace(1) %arg ret void } ; GCN: ScratchSize: 0 ; Should spill agprs to memory for both gfx908 and gfx90a. define amdgpu_kernel void @max_6regs_used_8a(ptr addrspace(1) %arg) #4 { ; GFX908-LABEL: max_6regs_used_8a: ; GFX908: ; %bb.0: ; GFX908-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX908-NEXT: ;;#ASMSTART ; GFX908-NEXT: ; def v1 ; GFX908-NEXT: ;;#ASMEND ; GFX908-NEXT: v_lshlrev_b32_e32 v4, 4, v0 ; GFX908-NEXT: ;;#ASMSTART ; GFX908-NEXT: ; def a[0:3] ; GFX908-NEXT: ;;#ASMEND ; GFX908-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GFX908-NEXT: v_accvgpr_write_b32 a4, v1 ; GFX908-NEXT: s_waitcnt lgkmcnt(0) ; GFX908-NEXT: global_load_dwordx4 v[0:3], v4, s[2:3] ; GFX908-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; GFX908-NEXT: s_mov_b32 s10, -1 ; GFX908-NEXT: s_mov_b32 s11, 0xe00000 ; GFX908-NEXT: s_add_u32 s8, s8, s5 ; GFX908-NEXT: s_addc_u32 s9, s9, 0 ; GFX908-NEXT: v_accvgpr_read_b32 v5, a0 ; Reload Reuse ; GFX908-NEXT: s_nop 1 ; GFX908-NEXT: buffer_store_dword v5, off, s[8:11], 0 ; 4-byte Folded Spill ; GFX908-NEXT: v_accvgpr_read_b32 v5, a1 ; Reload Reuse ; GFX908-NEXT: s_nop 1 ; GFX908-NEXT: buffer_store_dword v5, off, s[8:11], 0 offset:4 ; 4-byte Folded Spill ; GFX908-NEXT: v_accvgpr_read_b32 v5, a2 ; Reload Reuse ; GFX908-NEXT: s_nop 1 ; GFX908-NEXT: buffer_store_dword v5, off, s[8:11], 0 offset:8 ; 4-byte Folded Spill ; GFX908-NEXT: v_accvgpr_read_b32 v5, a3 ; Reload Reuse ; GFX908-NEXT: s_nop 1 ; GFX908-NEXT: buffer_store_dword v5, off, s[8:11], 0 offset:12 ; 4-byte Folded Spill ; GFX908-NEXT: s_waitcnt vmcnt(4) ; GFX908-NEXT: v_accvgpr_write_b32 a0, v0 ; GFX908-NEXT: v_accvgpr_write_b32 a1, v1 ; GFX908-NEXT: v_accvgpr_write_b32 a2, v2 ; GFX908-NEXT: v_accvgpr_write_b32 a3, v3 ; GFX908-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX908-NEXT: s_nop 1 ; GFX908-NEXT: v_mfma_f32_4x4x1f32 a[0:3], v0, v0, a[0:3] ; GFX908-NEXT: s_nop 3 ; GFX908-NEXT: v_accvgpr_read_b32 v0, a0 ; GFX908-NEXT: v_accvgpr_read_b32 v1, a1 ; GFX908-NEXT: v_accvgpr_read_b32 v2, a2 ; GFX908-NEXT: v_accvgpr_read_b32 v3, a3 ; GFX908-NEXT: s_nop 1 ; GFX908-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX908-NEXT: buffer_load_dword v0, off, s[8:11], 0 ; 4-byte Folded Reload ; GFX908-NEXT: s_nop 0 ; GFX908-NEXT: buffer_load_dword v1, off, s[8:11], 0 offset:4 ; 4-byte Folded Reload ; GFX908-NEXT: buffer_load_dword v2, off, s[8:11], 0 offset:8 ; 4-byte Folded Reload ; GFX908-NEXT: buffer_load_dword v3, off, s[8:11], 0 offset:12 ; 4-byte Folded Reload ; GFX908-NEXT: s_waitcnt vmcnt(0) ; GFX908-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GFX908-NEXT: s_waitcnt vmcnt(0) ; GFX908-NEXT: v_accvgpr_read_b32 v0, a4 ; GFX908-NEXT: ;;#ASMSTART ; GFX908-NEXT: ; use v0 ; GFX908-NEXT: ;;#ASMEND ; GFX908-NEXT: s_endpgm ; ; GFX90A-LABEL: max_6regs_used_8a: ; GFX90A: ; %bb.0: ; GFX90A-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GFX90A-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; GFX90A-NEXT: s_mov_b32 s10, -1 ; GFX90A-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX90A-NEXT: s_mov_b32 s11, 0xe00000 ; GFX90A-NEXT: s_add_u32 s8, s8, s5 ; GFX90A-NEXT: s_addc_u32 s9, s9, 0 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def v1 ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def a[0:3] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_store_dword a0, off, s[8:11], 0 ; 4-byte Folded Spill ; GFX90A-NEXT: s_nop 0 ; GFX90A-NEXT: buffer_store_dword a1, off, s[8:11], 0 offset:4 ; 4-byte Folded Spill ; GFX90A-NEXT: buffer_store_dword a2, off, s[8:11], 0 offset:8 ; 4-byte Folded Spill ; GFX90A-NEXT: buffer_store_dword a3, off, s[8:11], 0 offset:12 ; 4-byte Folded Spill ; GFX90A-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: global_load_dwordx4 a[0:3], v0, s[2:3] ; GFX90A-NEXT: v_mov_b32_e32 v2, 1.0 ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_nop 0 ; GFX90A-NEXT: v_mfma_f32_4x4x1f32 a[0:3], v2, v2, a[0:3] ; GFX90A-NEXT: buffer_load_dword v2, off, s[8:11], 0 ; 4-byte Folded Reload ; GFX90A-NEXT: buffer_load_dword v3, off, s[8:11], 0 offset:4 ; 4-byte Folded Reload ; GFX90A-NEXT: buffer_load_dword v4, off, s[8:11], 0 offset:8 ; 4-byte Folded Reload ; GFX90A-NEXT: buffer_load_dword v5, off, s[8:11], 0 offset:12 ; 4-byte Folded Reload ; GFX90A-NEXT: s_nop 0 ; GFX90A-NEXT: global_store_dwordx4 v0, a[0:3], s[2:3] ; GFX90A-NEXT: s_waitcnt vmcnt(1) ; GFX90A-NEXT: global_store_dwordx4 v[0:1], v[2:5], off ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use v1 ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %v0 = call float asm sideeffect "; def $0", "=v"() %a4 = call <4 x float> asm sideeffect "; def $0", "=a"() %gep = getelementptr inbounds <4 x float>, ptr addrspace(1) %arg, i32 %tid %mai.in = load <4 x float>, ptr addrspace(1) %gep %mai.out = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 1.0, <4 x float> %mai.in, i32 0, i32 0, i32 0) store <4 x float> %mai.out, ptr addrspace(1) %gep store volatile <4 x float> %a4, ptr addrspace(1) poison call void asm sideeffect "; use $0", "v"(float %v0); ret void } ; GCN: ScratchSize: 20 declare i32 @llvm.amdgcn.workitem.id.x() declare <16 x float> @llvm.amdgcn.mfma.f32.16x16x1f32(float, float, <16 x float>, i32, i32, i32) declare <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float, float, <4 x float>, i32, i32, i32) declare <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float, float, <32 x float>, i32, i32, i32) attributes #1 = { nounwind "amdgpu-num-vgpr"="10" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-cluster-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-cluster-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-cluster-id-z" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" } attributes #2 = { nounwind "amdgpu-num-vgpr"="12" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-cluster-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-cluster-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-cluster-id-z" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" } attributes #3 = { nounwind "amdgpu-num-vgpr"="32" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-cluster-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-cluster-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-cluster-id-z" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" } attributes #4 = { nounwind "amdgpu-num-vgpr"="6" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-cluster-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-cluster-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-cluster-id-z" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" } attributes #1 = { nounwind "amdgpu-num-vgpr"="10" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" } attributes #2 = { nounwind "amdgpu-num-vgpr"="12" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" } attributes #3 = { nounwind "amdgpu-num-vgpr"="32" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" } attributes #4 = { nounwind "amdgpu-num-vgpr"="6" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GCN: {{.*}}