# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# Test: fixVcmpxPermlaneHazards + S_SET_VGPR_MSB interaction on GFX1250
#
# Proves that VGPR lowering MUST run AFTER the hazard recognizer.
#
# fixVcmpxPermlaneHazards creates V_MOV_B32 Reg, Reg using permlane's src0.
# When src0 is a high VGPR (>= v256) but vdst is a low VGPR, the V_MOV_B32
# needs {dst=1, src0=1} MSB mode, while the permlane needs {dst=0, src0=1}.
#
# Current order (hazard-rec then vgpr-lowering): VGPR lowering sees the
# V_MOV_B32 and inserts S_SET_VGPR_MSB with correct {dst=1, src0=1}.
#
# Reversed order (vgpr-lowering then hazard-rec): The V_MOV_B32 inherits the
# permlane's {dst=0, src0=1}, causing it to write to v44 instead of v300.

# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=post-RA-hazard-rec,amdgpu-lower-vgpr-encoding -o - %s | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -start-before=post-RA-hazard-rec -o - %s | FileCheck -check-prefix=ASM %s

# vcmpx + permlane with high VGPR src0 ($vgpr300) and low VGPR vdst ($vgpr0).
# fixVcmpxPermlaneHazards inserts V_MOV_B32 $vgpr300, $vgpr300 before permlane.
#
# With correct order (hazard-rec then vgpr-lowering), VGPR lowering sees the
# V_MOV_B32 and inserts S_SET_VGPR_MSB 65 {dst=1, src0=1} before it,
# then S_SET_VGPR_MSB {dst=0, src0=1} before the permlane.
#
# If the order were reversed (vgpr-lowering then hazard-rec), VGPR lowering
# would only see the permlane and insert S_SET_VGPR_MSB 1 {dst=0, src0=1}.
# The V_MOV_B32 inserted later by the hazard recognizer would inherit dst=0,
# writing to v44 (300 & 0xFF) instead of v300.
#
# ASM-LABEL: vcmpx_permlane_high_vgpr_src0:
# ASM:      v_cmpx_le_f32_e32 0, v0
# ASM:      s_set_vgpr_msb 0x41
# ASM-NEXT: v_mov_b32_e32 v44 /*v300*/, v44 /*v300*/
# ASM-NEXT: s_set_vgpr_msb 0x4101
# ASM:      v_permlane16_b32 v0, v44 /*v300*/, s1, s0
---
name:            vcmpx_permlane_high_vgpr_src0
tracksRegLiveness: true
body:            |
  ; CHECK-LABEL: name: vcmpx_permlane_high_vgpr_src0
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $vgpr0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK-NEXT:   V_CMPX_LE_F32_nosdst_e32 0, $vgpr0, implicit-def $exec, implicit $mode, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   liveins: $vgpr0, $vgpr300, $sgpr0, $sgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   S_SET_VGPR_MSB 65, implicit-def $mode
  ; CHECK-NEXT:   $vgpr300 = V_MOV_B32_e32 killed $vgpr300, implicit $exec
  ; CHECK-NEXT:   S_SET_VGPR_MSB 16641, implicit-def $mode
  ; CHECK-NEXT:   $vgpr0 = V_PERMLANE16_B32_e64 0, killed $vgpr300, 0, killed $sgpr1, 0, killed $sgpr0, $vgpr0, 0, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    successors: %bb.1
    liveins: $vgpr0
    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    V_CMPX_LE_F32_nosdst_e32 0, $vgpr0, implicit-def $exec, implicit $mode, implicit $exec
    S_BRANCH %bb.1

  bb.1:
    liveins: $vgpr0, $vgpr300, $sgpr0, $sgpr1
    $vgpr0 = V_PERMLANE16_B32_e64 0, killed $vgpr300, 0, killed $sgpr1, 0, killed $sgpr0, $vgpr0, 0, implicit $exec
    S_ENDPGM 0
...