; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck %s

; On gfx90a, a 32-bit FLAT load may land in AV_32 (VGPR/AGPR). When passed
; inreg to an amdgpu_cs_chain_preserve call, SIInstrInfo must copy the
; ScalarOp into a VGPR-only class before v_readfirstlane_b32; otherwise
; -verify-machineinstrs rejects it.

@G = global ptr addrspace(3) poison

declare amdgpu_cs_chain_preserve void @callee(ptr addrspace(3) inreg, ptr addrspace(3))

define amdgpu_cs_chain_preserve void @caller() {
; CHECK-LABEL: caller:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_getpc_b64 s[0:1]
; CHECK-NEXT:    s_add_u32 s0, s0, G@gotpcrel32@lo+4
; CHECK-NEXT:    s_addc_u32 s1, s1, G@gotpcrel32@hi+12
; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
; CHECK-NEXT:    s_mov_b32 s54, s15
; CHECK-NEXT:    s_mov_b32 s55, s14
; CHECK-NEXT:    s_mov_b32 s64, s13
; CHECK-NEXT:    s_mov_b32 s65, s12
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; CHECK-NEXT:    flat_load_dword v0, v[0:1]
; CHECK-NEXT:    s_mov_b64 s[34:35], s[10:11]
; CHECK-NEXT:    s_mov_b64 s[36:37], s[8:9]
; CHECK-NEXT:    s_mov_b64 s[38:39], s[6:7]
; CHECK-NEXT:    s_mov_b64 s[52:53], s[4:5]
; CHECK-NEXT:    s_mov_b64 s[0:1], exec
; CHECK-NEXT:  .LBB0_1: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_readfirstlane_b32 s16, v0
; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, s16, v0
; CHECK-NEXT:    s_and_saveexec_b64 s[66:67], vcc
; CHECK-NEXT:    s_getpc_b64 s[0:1]
; CHECK-NEXT:    s_add_u32 s0, s0, callee@gotpcrel32@lo+4
; CHECK-NEXT:    s_addc_u32 s1, s1, callee@gotpcrel32@hi+12
; CHECK-NEXT:    s_load_dwordx2 s[18:19], s[0:1], 0x0
; CHECK-NEXT:    s_mov_b64 s[0:1], s[48:49]
; CHECK-NEXT:    s_mov_b64 s[2:3], s[50:51]
; CHECK-NEXT:    s_mov_b64 s[4:5], s[52:53]
; CHECK-NEXT:    s_mov_b64 s[6:7], s[38:39]
; CHECK-NEXT:    s_mov_b64 s[8:9], s[36:37]
; CHECK-NEXT:    s_mov_b64 s[10:11], s[34:35]
; CHECK-NEXT:    s_mov_b32 s12, s65
; CHECK-NEXT:    s_mov_b32 s13, s64
; CHECK-NEXT:    s_mov_b32 s14, s55
; CHECK-NEXT:    s_mov_b32 s15, s54
; CHECK-NEXT:    s_mov_b32 s0, s16
; CHECK-NEXT:    ; implicit-def: $vgpr0
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    s_swappc_b64 s[30:31], s[18:19]
; CHECK-NEXT:    ; implicit-def: $vgpr0
; CHECK-NEXT:    ; implicit-def: $vgpr31
; CHECK-NEXT:    s_xor_b64 exec, exec, s[66:67]
; CHECK-NEXT:    s_cbranch_execnz .LBB0_1
; CHECK-NEXT:  ; %bb.2:
; CHECK-NEXT:    s_endpgm
  %p = load ptr addrspace(3), ptr @G, align 4
  call void @callee(ptr addrspace(3) %p, ptr addrspace(3) poison)
  ret void
}