# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=si-wqm -verify-machineinstrs -o - %s | FileCheck %s

# Make sure the sources of execz side-effect instruction are calculated under wqm too.
--- |
  define amdgpu_ps float @execz_side_effect_wqm_propagation(float %FragCoordY, i32 %arg, i1 %arg1) {
  .entry:
    ret float poison
  }
...

---
name:            execz_side_effect_wqm_propagation
alignment:       4
tracksRegLiveness: true
noPhis:          true
isSSA:           false
machineFunctionInfo:
  isEntryFunction: true
  returnsVoid:     false
body:             |
  ; CHECK-LABEL: name: execz_side_effect_wqm_propagation
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.8(0x40000000)
  ; CHECK-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $exec_lo
  ; CHECK-NEXT:   $exec_lo = S_WQM_B32 $exec_lo, implicit-def $scc
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK-NEXT:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 1, [[COPY1]], implicit $exec
  ; CHECK-NEXT:   [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 1, [[V_AND_B32_e64_]], implicit $exec
  ; CHECK-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $exec_lo, implicit-def $exec_lo
  ; CHECK-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY4]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
  ; CHECK-NEXT:   $exec_lo = S_MOV_B32_term [[S_AND_B32_]]
  ; CHECK-NEXT:   S_CBRANCH_EXECZ %bb.8, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.5(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 0
  ; CHECK-NEXT:   [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = COPY [[S_MOV_B32_]].sub0
  ; CHECK-NEXT:   [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_128 = COPY [[S_MOV_B32_]].sub0
  ; CHECK-NEXT:   [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_128 = COPY [[S_MOV_B32_]].sub0
  ; CHECK-NEXT:   undef [[COPY5:%[0-9]+]].sub0:sgpr_256 = COPY [[S_MOV_B32_]].sub0
  ; CHECK-NEXT:   [[COPY5:%[0-9]+]].sub1:sgpr_256 = COPY [[S_MOV_B32_]].sub0
  ; CHECK-NEXT:   [[COPY5:%[0-9]+]].sub2:sgpr_256 = COPY [[S_MOV_B32_]].sub0
  ; CHECK-NEXT:   [[COPY5:%[0-9]+]].sub3:sgpr_256 = COPY [[S_MOV_B32_]].sub0
  ; CHECK-NEXT:   [[COPY5:%[0-9]+]].sub4:sgpr_256 = COPY [[S_MOV_B32_]].sub0
  ; CHECK-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK-NEXT:   [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32 = S_AND_SAVEEXEC_B32 [[COPY]], implicit-def $exec, implicit-def $scc, implicit $exec
  ; CHECK-NEXT:   [[COPY5:%[0-9]+]].sub5:sgpr_256 = COPY [[S_MOV_B32_]].sub0
  ; CHECK-NEXT:   [[COPY5:%[0-9]+]].sub6:sgpr_256 = COPY [[S_MOV_B32_]].sub0
  ; CHECK-NEXT:   [[COPY5:%[0-9]+]].sub7:sgpr_256 = COPY [[S_MOV_B32_]].sub0
  ; CHECK-NEXT:   [[IMAGE_SAMPLE_V1_V3_gfx12_:%[0-9]+]]:vgpr_32 = IMAGE_SAMPLE_V1_V3_gfx12 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], [[COPY3]], [[COPY5]], [[S_MOV_B32_]], 1, 3, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
  ; CHECK-NEXT:   IMAGE_ATOMIC_ADD_NORTN_V1_V2_gfx12 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], [[COPY5]], 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s32), addrspace 8)
  ; CHECK-NEXT:   $exec_lo = COPY [[S_AND_SAVEEXEC_B32_]]
  ; CHECK-NEXT:   [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
  ; CHECK-NEXT:   [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (s32))
  ; CHECK-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[V_MED3_F32_e64_]], implicit $exec
  ; CHECK-NEXT:   [[S_MUL_F32_:%[0-9]+]]:sgpr_32 = nofpexcept S_MUL_F32 [[V_READFIRSTLANE_B32_]], 0, implicit $mode
  ; CHECK-NEXT:   [[S_MUL_F32_1:%[0-9]+]]:sgpr_32 = nofpexcept S_MUL_F32 [[S_MUL_F32_]], 0, implicit $mode
  ; CHECK-NEXT:   [[S_CVT_I32_F32_:%[0-9]+]]:sreg_32 = nofpexcept S_CVT_I32_F32 [[S_MUL_F32_1]], implicit $mode
  ; CHECK-NEXT:   [[V_CVT_I32_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e64 0, [[IMAGE_SAMPLE_V1_V3_gfx12_]], 0, 0, implicit $mode, implicit $exec
  ; CHECK-NEXT:   [[V_MUL_LO_U32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32_e64 [[S_BUFFER_LOAD_DWORD_IMM]], [[COPY2]], implicit $exec
  ; CHECK-NEXT:   [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[S_CVT_I32_F32_]], 8, implicit-def dead $scc
  ; CHECK-NEXT:   undef [[V_OR_B16_t16_e64_:%[0-9]+]].lo16:vreg_128 = V_OR_B16_t16_e64 0, [[V_CVT_I32_F32_e64_]].lo16, 0, [[S_LSHL_B32_]], 0, implicit $exec
  ; CHECK-NEXT:   [[V_OR_B16_t16_e64_:%[0-9]+]].hi16:vreg_128 = V_MOV_B16_t16_e64 0, 0, 0, implicit $exec
  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $exec_lo, implicit-def $exec_lo
  ; CHECK-NEXT:   [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY6]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
  ; CHECK-NEXT:   [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[S_AND_B32_1]], [[COPY6]], implicit-def dead $scc
  ; CHECK-NEXT:   $exec_lo = S_MOV_B32_term [[S_AND_B32_1]]
  ; CHECK-NEXT:   S_CBRANCH_EXECZ %bb.2, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.5
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   successors: %bb.3(0x40000000), %bb.7(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[S_OR_SAVEEXEC_B32_:%[0-9]+]]:sreg_32 = S_OR_SAVEEXEC_B32 [[S_XOR_B32_]], implicit-def $exec, implicit-def $scc, implicit $exec
  ; CHECK-NEXT:   [[S_AND_B32_2:%[0-9]+]]:sreg_32 = S_AND_B32 $exec_lo, [[S_OR_SAVEEXEC_B32_]], implicit-def $scc
  ; CHECK-NEXT:   $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_B32_2]], implicit-def $scc
  ; CHECK-NEXT:   S_CBRANCH_EXECZ %bb.7, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   successors: %bb.4(0x40000000), %bb.6(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 0
  ; CHECK-NEXT:   [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_128 = COPY [[S_MOV_B32_1]].sub0
  ; CHECK-NEXT:   [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_128 = COPY [[S_MOV_B32_1]].sub0
  ; CHECK-NEXT:   [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_128 = COPY [[S_MOV_B32_1]].sub0
  ; CHECK-NEXT:   [[BUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN [[V_MUL_LO_U32_e64_]], [[S_MOV_B32_1]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (s64), align 1, addrspace 8)
  ; CHECK-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK-NEXT:   [[V_CMP_LT_F32_e64_:%[0-9]+]]:sreg_32 = nofpexcept V_CMP_LT_F32_e64 0, 0, 0, [[BUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN]].sub0, 0, implicit $mode, implicit $exec
  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $exec_lo, implicit-def $exec_lo
  ; CHECK-NEXT:   [[S_AND_B32_3:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY7]], [[V_CMP_LT_F32_e64_]], implicit-def dead $scc
  ; CHECK-NEXT:   $exec_lo = S_MOV_B32_term [[S_AND_B32_3]]
  ; CHECK-NEXT:   S_CBRANCH_EXECZ %bb.6, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.4
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.4:
  ; CHECK-NEXT:   successors: %bb.6(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = COPY [[V_OR_B16_t16_e64_]].sub0
  ; CHECK-NEXT:   S_BRANCH %bb.6
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.5:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[S_AND_SAVEEXEC_B32_1:%[0-9]+]]:sreg_32 = S_AND_SAVEEXEC_B32 [[COPY]], implicit-def $exec, implicit-def $scc, implicit $exec
  ; CHECK-NEXT:   [[V_OR_B16_t16_e64_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK-NEXT:   [[V_OR_B16_t16_e64_:%[0-9]+]].sub2:vreg_128 = COPY [[V_OR_B16_t16_e64_]].sub1
  ; CHECK-NEXT:   [[V_OR_B16_t16_e64_:%[0-9]+]].sub3:vreg_128 = COPY [[V_OR_B16_t16_e64_]].sub1
  ; CHECK-NEXT:   BUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_exact [[V_OR_B16_t16_e64_]], [[V_MUL_LO_U32_e64_]], [[S_MOV_B32_]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable store (s128), align 1, addrspace 8)
  ; CHECK-NEXT:   [[V_MUL_LO_U32_e64_:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   undef [[V_OR_B16_t16_e64_:%[0-9]+]].sub0:vreg_128 = IMPLICIT_DEF
  ; CHECK-NEXT:   $exec_lo = COPY [[S_AND_SAVEEXEC_B32_1]]
  ; CHECK-NEXT:   S_BRANCH %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.6:
  ; CHECK-NEXT:   successors: %bb.7(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $exec_lo = S_OR_B32 $exec_lo, [[COPY7]], implicit-def $scc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.7:
  ; CHECK-NEXT:   successors: %bb.8(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $exec_lo = S_OR_B32 $exec_lo, [[S_AND_B32_2]], implicit-def $scc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.8:
  ; CHECK-NEXT:   $exec_lo = S_OR_B32 $exec_lo, [[COPY4]], implicit-def $scc
  ; CHECK-NEXT:   $exec_lo = S_AND_B32 $exec_lo, [[COPY]], implicit-def $scc
  ; CHECK-NEXT:   $vgpr0 = COPY [[V_MOV_B32_e32_]]
  ; CHECK-NEXT:   SI_RETURN_TO_EPILOG $vgpr0
  bb.0:
    successors: %bb.1, %bb.8
    liveins: $vgpr0, $vgpr1, $vgpr2

    %2:vgpr_32 = COPY $vgpr2
    %1:vgpr_32 = COPY $vgpr1
    %0:vgpr_32 = COPY $vgpr0
    %3:vgpr_32 = V_AND_B32_e64 1, %2, implicit $exec
    %4:sreg_32 = V_CMP_NE_U32_e64 1, %3, implicit $exec
    %5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    %6:sreg_32 = COPY $exec_lo, implicit-def $exec_lo
    %7:sreg_32 = S_AND_B32 %6, %4, implicit-def dead $scc
    $exec_lo = S_MOV_B32_term %7
    S_CBRANCH_EXECZ %bb.8, implicit $exec
    S_BRANCH %bb.1

  bb.1:
    successors: %bb.5, %bb.2

    undef %8.sub0:sgpr_128 = S_MOV_B32 0
    %8.sub1:sgpr_128 = COPY %8.sub0
    %8.sub2:sgpr_128 = COPY %8.sub0
    %8.sub3:sgpr_128 = COPY %8.sub0
    undef %9.sub0:sgpr_256 = COPY %8.sub0
    %9.sub1:sgpr_256 = COPY %8.sub0
    %9.sub2:sgpr_256 = COPY %8.sub0
    %9.sub3:sgpr_256 = COPY %8.sub0
    %9.sub4:sgpr_256 = COPY %8.sub0
    %5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    %9.sub5:sgpr_256 = COPY %8.sub0
    %9.sub6:sgpr_256 = COPY %8.sub0
    %9.sub7:sgpr_256 = COPY %8.sub0
    %10:vgpr_32 = IMAGE_SAMPLE_V1_V3_gfx12 %5, %5, %0, %9, %8, 1, 3, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
    IMAGE_ATOMIC_ADD_NORTN_V1_V2_gfx12 %5, %5, %5, %9, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s32), addrspace 8)
    %11:vgpr_32 = V_MED3_F32_e64 0, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
    %12:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM %8, 0, 0 :: (dereferenceable invariant load (s32))
    %13:sreg_32_xm0 = V_READFIRSTLANE_B32 %11, implicit $exec
    %14:sgpr_32 = nofpexcept S_MUL_F32 %13, 0, implicit $mode
    %15:sgpr_32 = nofpexcept S_MUL_F32 %14, 0, implicit $mode
    %16:sreg_32 = nofpexcept S_CVT_I32_F32 %15, implicit $mode
    %17:vgpr_32 = nofpexcept V_CVT_I32_F32_e64 0, %10, 0, 0, implicit $mode, implicit $exec
    %18:vgpr_32 = V_MUL_LO_U32_e64 %12, %1, implicit $exec
    %19:sreg_32 = S_LSHL_B32 %16, 8, implicit-def dead $scc
    undef %20.lo16:vreg_128 = V_OR_B16_t16_e64 0, %17.lo16, 0, %19, 0, implicit $exec
    %20.hi16:vreg_128 = V_MOV_B16_t16_e64 0, 0, 0, implicit $exec
    %21:sreg_32 = COPY $exec_lo, implicit-def $exec_lo
    %22:sreg_32 = S_AND_B32 %21, %4, implicit-def dead $scc
    %23:sreg_32 = S_XOR_B32 %22, %21, implicit-def dead $scc
    $exec_lo = S_MOV_B32_term %22
    S_CBRANCH_EXECZ %bb.2, implicit $exec
    S_BRANCH %bb.5

  bb.2:
    successors: %bb.3, %bb.7

    %24:sreg_32 = S_OR_SAVEEXEC_B32 %23, implicit-def $exec, implicit-def $scc, implicit $exec
    %25:sreg_32 = S_AND_B32 $exec_lo, %24, implicit-def $scc
    $exec_lo = S_XOR_B32_term $exec_lo, %25, implicit-def $scc
    S_CBRANCH_EXECZ %bb.7, implicit $exec
    S_BRANCH %bb.3

  bb.3:
    successors: %bb.4, %bb.6

    undef %26.sub0:sgpr_128 = S_MOV_B32 0
    %26.sub1:sgpr_128 = COPY %26.sub0
    %26.sub2:sgpr_128 = COPY %26.sub0
    %26.sub3:sgpr_128 = COPY %26.sub0
    %27:vreg_64 = BUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN %18, %26, $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable load (s64), align 1, addrspace 8)
    %5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    %28:sreg_32 = nofpexcept V_CMP_LT_F32_e64 0, 0, 0, %27.sub0, 0, implicit $mode, implicit $exec
    %29:sreg_32 = COPY $exec_lo, implicit-def $exec_lo
    %30:sreg_32 = S_AND_B32 %29, %28, implicit-def dead $scc
    $exec_lo = S_MOV_B32_term %30
    S_CBRANCH_EXECZ %bb.6, implicit $exec
    S_BRANCH %bb.4

  bb.4:
    %5:vgpr_32 = COPY %20.sub0
    S_BRANCH %bb.6

  bb.5:
    %20.sub1:vreg_128 = V_MOV_B32_e32 0, implicit $exec
    %20.sub2:vreg_128 = COPY %20.sub1
    %20.sub3:vreg_128 = COPY %20.sub1
    BUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_exact %20, %18, %8, $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable store (s128), align 1, addrspace 8)
    %18:vgpr_32 = IMPLICIT_DEF
    undef %20.sub0:vreg_128 = IMPLICIT_DEF
    S_BRANCH %bb.2

  bb.6:
    $exec_lo = S_OR_B32 $exec_lo, %29, implicit-def $scc

  bb.7:
    $exec_lo = S_OR_B32 $exec_lo, %25, implicit-def $scc

  bb.8:
    $exec_lo = S_OR_B32 $exec_lo, %6, implicit-def $scc
    $vgpr0 = COPY %5
    SI_RETURN_TO_EPILOG $vgpr0
...