; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
; rdar://11035895

; DAG combine incorrectly optimize (i32 vextract (v4i16 load $addr), c) to
; (i16 load $addr+c*sizeof(i16)). It should have issued an extload instead. i.e.
; (i32 extload $addr+c*sizeof(i16)
define void @test_hi_short3(ptr nocapture %srcA, ptr nocapture %dst) nounwind {
; CHECK-LABEL: test_hi_short3:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vldr d16, [r0]
; CHECK-NEXT:    vmov.u16 r0, d16[2]
; CHECK-NEXT:    vmov.32 d16[0], r0
; CHECK-NEXT:    vuzp.16 d16, d17
; CHECK-NEXT:    vst1.32 {d16[0]}, [r1:32]
; CHECK-NEXT:    bx lr
entry:
  %0 = load <3 x i16> , ptr %srcA, align 8
  %1 = shufflevector <3 x i16> %0, <3 x i16> undef, <2 x i32> <i32 2, i32 undef>
  store <2 x i16> %1, ptr %dst, align 4
  ret void
}