; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=hexagon -mattr=+hvxv69,+hvx-length128b < %s | FileCheck %s
; RUN: llc -mtriple=hexagon -mattr=+hvxv73,+hvx-length128b < %s | FileCheck %s

; Regression test for crash in TargetLowering::expandCttzElts.
;
; expandCttzElts() did not handle the empty StepVec returned by
; getLegalMaskAndStepVector() when the implied step-vector type
; required TypeSplitVector, causing a null SDValue dereference.

define i32 @ctz_v32i1(<32 x i1> %m) {
; CHECK-LABEL: ctz_v32i1:
; CHECK:         .cfi_startproc
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    {
; CHECK-NEXT:     r1:0 = combine(#-1,##16843009)
; CHECK-NEXT:     r4 = #0
; CHECK-NEXT:     allocframe(r29,#640):raw
; CHECK-NEXT:    }
; CHECK-NEXT:    .cfi_def_cfa r30, 8
; CHECK-NEXT:    .cfi_offset r31, -4
; CHECK-NEXT:    .cfi_offset r30, -8
; CHECK-NEXT:    .cfi_offset r17, -12
; CHECK-NEXT:    .cfi_offset r16, -16
; CHECK-NEXT:    .cfi_offset r19, -20
; CHECK-NEXT:    .cfi_offset r18, -24
; CHECK-NEXT:    .cfi_offset r21, -28
; CHECK-NEXT:    .cfi_offset r20, -32
; CHECK-NEXT:    {
; CHECK-NEXT:     q0 = vand(v0,r0)
; CHECK-NEXT:     r29 = and(r29,#-128)
; CHECK-NEXT:     r3:2 = CONST64(#72623859790382856)
; CHECK-NEXT:     memd(r30+#-8) = r17:16
; CHECK-NEXT:    } // 8-byte Folded Spill
; CHECK-NEXT:    {
; CHECK-NEXT:     v0 = vand(q0,r1)
; CHECK-NEXT:     r8 = add(r29,#128)
; CHECK-NEXT:     memd(r30+#-16) = r19:18
; CHECK-NEXT:     memd(r30+#-24) = r21:20
; CHECK-NEXT:    } // 8-byte Folded Spill
; CHECK-NEXT:    {
; CHECK-NEXT:     r5:4 = vsplatb(r4)
; CHECK-NEXT:     r0 = #8
; CHECK-NEXT:     vmem(r8+#0) = v0
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r6 = ##.LCPI0_0
; CHECK-NEXT:     r7 = add(r29,#256)
; CHECK-NEXT:     r1 = memw(r8+#104)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r6 = ##.LCPI0_1
; CHECK-NEXT:     r9 = memw(r8+#108)
; CHECK-NEXT:     v1 = vmem(r6+#0)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r12 = and(r1,#255)
; CHECK-NEXT:     r1 = add(r29,#384)
; CHECK-NEXT:     r13 = memw(r8+#96)
; CHECK-NEXT:     r17 = memw(r8+#100)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     p0 = cmp.gtu(r12,#0)
; CHECK-NEXT:     r9 = and(r9,#255)
; CHECK-NEXT:     r19 = memw(r8+#120)
; CHECK-NEXT:     r14 = memw(r8+#124)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r15 = and(r17,#255)
; CHECK-NEXT:     r20 = and(r19,#255)
; CHECK-NEXT:     r10 = memw(r8+#112)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r21 = and(r10,#255)
; CHECK-NEXT:     r28 = and(r14,#255)
; CHECK-NEXT:     r10 = memw(r8+#116)
; CHECK-NEXT:     r11 = memw(r8+#72)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r12 = p0
; CHECK-NEXT:     r17 = and(r10,#255)
; CHECK-NEXT:     p3 = cmp.gtu(r15,#0)
; CHECK-NEXT:     r19 = memw(r8+#76)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     p1 = cmp.gtu(r9,#0)
; CHECK-NEXT:     p0 = cmp.gtu(r28,#0)
; CHECK-NEXT:     r10 = and(r19,#255)
; CHECK-NEXT:     p2 = cmp.gtu(r17,#0)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r18 = r12
; CHECK-NEXT:     r28 = mux(p3,#2,#0)
; CHECK-NEXT:     p3 = cmp.gtu(r10,#0)
; CHECK-NEXT:     r12 = and(r13,#255)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r9 = mux(p1,#8,#0)
; CHECK-NEXT:     r10 = mux(p2,#32,#0)
; CHECK-NEXT:     p2 = cmp.gtu(r20,#0)
; CHECK-NEXT:     r20 = r18
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r13 = setbit(r28,#0)
; CHECK-NEXT:     r15 = mux(p0,##128,#0)
; CHECK-NEXT:     p1 = cmp.gtu(r12,#0)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r17 = setbit(r9,#2)
; CHECK-NEXT:     p0 = r20
; CHECK-NEXT:     r16 = mux(p3,#8,#0)
; CHECK-NEXT:     p3 = cmp.gtu(r21,#0)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r14 = setbit(r15,#6)
; CHECK-NEXT:     r28 = setbit(r10,#4)
; CHECK-NEXT:     if (!p1) r13 = add(r28,#0)
; CHECK-NEXT:     if (!p0) r17 = add(r9,#0)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r19 = and(r11,#255)
; CHECK-NEXT:     r13 = or(r13,r17)
; CHECK-NEXT:     if (!p2) r14 = add(r15,#0)
; CHECK-NEXT:     r21 = memw(r8+#64)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r12 = setbit(r16,#2)
; CHECK-NEXT:     if (!p3) r28 = add(r10,#0)
; CHECK-NEXT:     p0 = cmp.gtu(r19,#0)
; CHECK-NEXT:     r11 = memw(r8+#68)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r13 |= or(r28,r14)
; CHECK-NEXT:     if (!p0) r12 = add(r16,#0)
; CHECK-NEXT:     r16 = and(r11,#255)
; CHECK-NEXT:     r10 = memw(r8+#88)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     p1 = r13
; CHECK-NEXT:     p0 = cmp.gtu(r16,#0)
; CHECK-NEXT:     r11 = memw(r8+#92)
; CHECK-NEXT:     r15 = memw(r8+#80)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r9:8 = vmux(p1,r3:2,r5:4)
; CHECK-NEXT:     r17 = and(r11,#255)
; CHECK-NEXT:     r18 = memw(r8+#84)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r17:16 = extractu(r9:8,#8,#16)
; CHECK-NEXT:     r28 = extractu(r8,#3,#8)
; CHECK-NEXT:     p1 = cmp.gtu(r17,#0)
; CHECK-NEXT:     r13 = and(r18,#255)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r17 = and(r8,r0)
; CHECK-NEXT:     r11 = mux(p0,#2,#0)
; CHECK-NEXT:     p0 = cmp.gtu(r13,#0)
; CHECK-NEXT:     r16 = and(r16,#6)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r28 = maxu(r17,r28)
; CHECK-NEXT:     r14 = and(r21,#255)
; CHECK-NEXT:     r10 = and(r10,#255)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r28 = maxu(r28,r16)
; CHECK-NEXT:     r14 = setbit(r11,#0)
; CHECK-NEXT:     p2 = cmp.gtu(r14,#0)
; CHECK-NEXT:     r16 = mux(p0,#32,#0)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r13 = mux(p1,##128,#0)
; CHECK-NEXT:     r15 = and(r15,#255)
; CHECK-NEXT:     if (!p2) r14 = add(r11,#0)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r10 = setbit(r13,#6)
; CHECK-NEXT:     r15 = setbit(r16,#4)
; CHECK-NEXT:     p0 = cmp.gtu(r10,#0)
; CHECK-NEXT:     p1 = cmp.gtu(r15,#0)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r19:18 = extractu(r9:8,#8,#24)
; CHECK-NEXT:     if (!p1) r15 = add(r16,#0)
; CHECK-NEXT:     r12 = or(r14,r12)
; CHECK-NEXT:     if (!p0) r10 = add(r13,#0)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r12 |= or(r15,r10)
; CHECK-NEXT:     r21:20 = extractu(r9:8,#8,#32)
; CHECK-NEXT:     r18 = and(r18,#5)
; CHECK-NEXT:     v1 = vrdelta(v0,v1)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r28 = maxu(r28,r18)
; CHECK-NEXT:     p0 = r12
; CHECK-NEXT:     r19 = and(r20,#4)
; CHECK-NEXT:     vmem(r7+#0) = v1
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r28 = maxu(r28,r19)
; CHECK-NEXT:     r13:12 = vmux(p0,r3:2,r5:4)
; CHECK-NEXT:     v31 = vmem(r6+#0)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r11 = extractu(r12,#3,#8)
; CHECK-NEXT:     r19 = extractu(r9,#2,#8)
; CHECK-NEXT:     r10 = and(r12,r0)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r15 = maxu(r10,r11)
; CHECK-NEXT:     r20 = maxu(r28,r19)
; CHECK-NEXT:     v0 = vrdelta(v0,v31)
; CHECK-NEXT:     r10 = memw(r7+#0)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r19:18 = extractu(r13:12,#8,#16)
; CHECK-NEXT:     r17:16 = extractu(r9:8,#8,#48)
; CHECK-NEXT:     r11 = memw(r7+#4)
; CHECK-NEXT:     vmem(r1+#0) = v0
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r19:18 = extractu(r13:12,#8,#32)
; CHECK-NEXT:     p0 = vcmpb.gtu(r11:10,#0)
; CHECK-NEXT:     r14 = and(r18,#6)
; CHECK-NEXT:     r21 = and(r16,#2)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r7 = maxu(r15,r14)
; CHECK-NEXT:     r15:14 = vmux(p0,r3:2,r5:4)
; CHECK-NEXT:     r19 = and(r18,#4)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r8 = maxu(r20,r21)
; CHECK-NEXT:     r21:20 = extractu(r13:12,#8,#24)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r17:16 = extractu(r15:14,#8,#16)
; CHECK-NEXT:     r21 = extractu(r14,#3,#8)
; CHECK-NEXT:     r28 = and(r20,#5)
; CHECK-NEXT:     r20 = and(r14,r0)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r7 = maxu(r7,r28)
; CHECK-NEXT:     r28 = maxu(r20,r21)
; CHECK-NEXT:     r18 = and(r16,#6)
; CHECK-NEXT:     r16 = memw(r1+#0)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r6 = maxu(r7,r19)
; CHECK-NEXT:     r7 = extractu(r13,#2,#8)
; CHECK-NEXT:     r17 = memw(r1+#4)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r21:20 = extractu(r15:14,#8,#24)
; CHECK-NEXT:     p0 = vcmpb.gtu(r17:16,#0)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r6 = maxu(r6,r7)
; CHECK-NEXT:     r3:2 = vmux(p0,r3:2,r5:4)
; CHECK-NEXT:     r7 = and(r20,#5)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r1 = maxu(r28,r18)
; CHECK-NEXT:     r21:20 = extractu(r13:12,#8,#48)
; CHECK-NEXT:     r0 = and(r2,r0)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r17:16 = extractu(r15:14,#8,#32)
; CHECK-NEXT:     r1 = maxu(r1,r7)
; CHECK-NEXT:     r4 = and(r20,#2)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r5 = extractu(r2,#3,#8)
; CHECK-NEXT:     r19:18 = extractu(r3:2,#8,#16)
; CHECK-NEXT:     r7 = and(r16,#4)
; CHECK-NEXT:     r17:16 = memd(r30+#-8)
; CHECK-NEXT:    } // 8-byte Folded Reload
; CHECK-NEXT:    {
; CHECK-NEXT:     r0 = maxu(r0,r5)
; CHECK-NEXT:     r4 = maxu(r6,r4)
; CHECK-NEXT:     r5 = and(r18,#6)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r1 = maxu(r1,r7)
; CHECK-NEXT:     r7:6 = extractu(r3:2,#8,#24)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r0 = maxu(r0,r5)
; CHECK-NEXT:     r7:6 = extractu(r3:2,#8,#32)
; CHECK-NEXT:     r5 = and(r6,#5)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r0 = maxu(r0,r5)
; CHECK-NEXT:     r19:18 = extractu(r3:2,#8,#48)
; CHECK-NEXT:     r6 = and(r6,#4)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r0 = maxu(r0,r6)
; CHECK-NEXT:     r6 = extractu(r3,#2,#8)
; CHECK-NEXT:     r5 = and(r18,#2)
; CHECK-NEXT:     r19:18 = memd(r30+#-16)
; CHECK-NEXT:    } // 8-byte Folded Reload
; CHECK-NEXT:    {
; CHECK-NEXT:     r0 = maxu(r0,r6)
; CHECK-NEXT:     r7 = extractu(r15,#2,#8)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r21:20 = extractu(r15:14,#8,#48)
; CHECK-NEXT:     r1 = maxu(r1,r7)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r0 = maxu(r0,r5)
; CHECK-NEXT:     r5 = extractu(r3,#1,#24)
; CHECK-NEXT:     r2 = and(r20,#2)
; CHECK-NEXT:     r21:20 = memd(r30+#-24)
; CHECK-NEXT:    } // 8-byte Folded Reload
; CHECK-NEXT:    {
; CHECK-NEXT:     r6 = extractu(r13,#1,#24)
; CHECK-NEXT:     r1 = maxu(r1,r2)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r3 = extractu(r15,#1,#24)
; CHECK-NEXT:     r0 = maxu(r0,r5)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r4 = maxu(r4,r6)
; CHECK-NEXT:     r7 = extractu(r9,#1,#24)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r1 = maxu(r1,r3)
; CHECK-NEXT:     r2 = maxu(r8,r7)
; CHECK-NEXT:     r3 = sub(#8,r0)
; CHECK-NEXT:     r4 = sub(#8,r4)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r0 = sub(#16,r1)
; CHECK-NEXT:     p0 = cmp.eq(r3,#8)
; CHECK-NEXT:     r1 = sub(#16,r2)
; CHECK-NEXT:     p1 = cmp.eq(r4,#8)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     if (!p0) r0 = add(r3,#0)
; CHECK-NEXT:     if (!p1) r1 = add(r4,#0)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     p0 = cmp.eq(r0,#16)
; CHECK-NEXT:     if (p0.new) r0 = add(r1,#16)
; CHECK-NEXT:     r31:30 = dealloc_return(r30):raw
; CHECK-NEXT:    }
  %res = call i32 @llvm.experimental.cttz.elts.i32.v32i1(<32 x i1> %m, i1 false)
  ret i32 %res
}