; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=hexagon -hexagon-hvx-widen=32 -hexagon-fp-fast-convert=true -mattr=+hvxv68,+hvx-length128b,+hvx-qfloat < %s | FileCheck %s --check-prefix=CHECK-V68
; RUN: llc -mtriple=hexagon -hexagon-hvx-widen=32 -hexagon-fp-fast-convert=true -mattr=+hvxv81,+hvx-length128b,+hvx-qfloat < %s | FileCheck %s --check-prefix=CHECK-V81

; ----------------------------
; V68 Tests
; ----------------------------

; f16 -> s16 (No widening)
define void @f16s16_0(ptr %a0, ptr %a1) #0 {
; CHECK-V68-LABEL: f16s16_0:
; CHECK-V68:       {
; CHECK-V68:       [[DST:v[0-9]+]].h = [[SRC:v[0-9]+]].hf
; CHECK-V68-NEXT:  jumpr r31
; CHECK-V68:       vmem(r1+#0) = [[DST]].new
; CHECK-V68-NEXT:  }
  %v0 = load <64 x half>, ptr %a0, align 128
  %v1 = fptosi <64 x half> %v0 to <64 x i16>
  store <64 x i16> %v1, ptr %a1, align 128
  ret void
}

; f32 -> s8 (Triggers V6_vconv_w_sf)
define void @f32s8_2(ptr %a0, ptr %a1) {
; CHECK-V68-LABEL: f32s8_2:
; CHECK-V68:       {
; CHECK-V68:       [[SRC:v[0-9]+]] = vmem(r0+#0)
; CHECK-V68:       [[SRC]].w = [[SRC]].sf
; CHECK-V68:       vpack
; CHECK-V68:       vpack
; CHECK-V68:       vpack
; CHECK-V68:       jumpr r31
; CHECK-V68:       vmem(r1+#0) = [[DST:v[0-9]+]]
; CHECK-V68-NEXT:  }
  %v0 = load <32 x float>, ptr %a0, align 128
  %v1 = fptosi <32 x float> %v0 to <32 x i8>
  store <32 x i8> %v1, ptr %a1, align 128
  ret void
}

; ----------------------------
; V81 Tests
; ----------------------------

; f16 -> s16 with rounding (V6_vconv_h_hf_rnd)
define void @f16s16_v81(ptr %a0, ptr %a1) {
; CHECK-V81-LABEL: f16s16_v81:
; CHECK-V81:       {
; CHECK-V81:       [[DST:v[0-9]+]].h = [[SRC:v[0-9]+]].hf:rnd
; CHECK-V81-NEXT:  jumpr r31
; CHECK-V81:       vmem(r1+#0) = [[DST]].new
; CHECK-V81-NEXT:  }
  %v0 = load <64 x half>, ptr %a0, align 128
  %v1 = fptosi <64 x half> %v0 to <64 x i16>
  store <64 x i16> %v1, ptr %a1, align 128
  ret void
}

; f32 -> s8 with V81 (still uses V6_vconv_w_sf)
define void @f32s8_v81(ptr %a0, ptr %a1) {
; CHECK-V81-LABEL: f32s8_v81:
; CHECK-V81:       {
; CHECK-V81:       [[SRC:v[0-9]+]] = vmem(r0+#0)
; CHECK-V81:       [[SRC]].w = [[SRC]].sf
; CHECK-V81:       vpack
; CHECK-V81:       vpack
; CHECK-V81:       vpack
; CHECK-V81:       jumpr r31
; CHECK-V81:       vmem(r1+#0) = [[DST:v[0-9]+]]
; CHECK-V81-NEXT:  }
  %v0 = load <32 x float>, ptr %a0, align 128
  %v1 = fptosi <32 x float> %v0 to <32 x i8>
  store <32 x i8> %v1, ptr %a1, align 128
  ret void
}