# RUN: llc -march=hexagon -mcpu=hexagonv69 -mattr=+hvxv69,+hvx-length128b -run-pass hexagon-qfp-optimizer %s -o - | FileCheck %s

# CHECK: V6_vshuffvdd
# CHECK: V6_vadd_sf
# CHECK: V6_vadd_qf32_mix{{.*}}vsub_lo
# CHECK: V6_vadd_qf32_mix{{.*}}vsub_hi

---
name:            qfp_subreg_fix
alignment:       16
tracksRegLiveness: true

body:             |
  bb.0:
    %10:intregs = IMPLICIT_DEF
    %9:hvxvr = V6_vL32Ub_ai %10, 0 :: (load (s1024) from `ptr undef`, align 4)
    %11:intregs = A2_tfrsi 15360
    %12:hvxvr = V6_lvsplath %11
    %13:hvxwr = V6_vmpy_qf32_hf %9, %12
    %15:hvxvr = V6_vconv_sf_qf32 %13.vsub_lo
    %17:hvxvr = V6_vconv_sf_qf32 %13.vsub_hi
    %18:intregslow8 = A2_tfrsi -4
    %19:hvxwr = V6_vshuffvdd %17, %15, %18
    %21:hvxvr = V6_vadd_sf %19.vsub_hi, %19.vsub_hi
    %22:hvxvr = V6_vconv_sf_qf32 %21
    %24:hvxvr = V6_vadd_sf %19.vsub_lo, %19.vsub_lo
    %25:hvxvr = V6_vconv_sf_qf32 %24
    %26:hvxvr = V6_vadd_sf %25, %19.vsub_lo
    %27:hvxvr = V6_vconv_sf_qf32 %26
    %28:hvxvr = V6_vadd_sf %22, %19.vsub_hi
    %29:hvxvr = V6_vconv_sf_qf32 %28

...