# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -o -| FileCheck %s

--- |
  define void @test_swp_ws_live_intervals(i32 %.pre) {
  entry:
    %cgep9 = bitcast ptr null to ptr
    br label %for.body147

  for.body147:                                      ; preds = %for.body170, %entry
    %add11.i526 = or i32 %.pre, 1
    br label %for.body158

  for.body158:                                      ; preds = %for.body158, %for.body147
    %lsr.iv = phi i32 [ %lsr.iv.next, %for.body158 ], [ -1, %for.body147 ]
    %add11.i536602603 = phi i32 [ %add11.i526, %for.body147 ], [ 0, %for.body158 ]
    %and8.i534 = and i32 %add11.i536602603, 1
    %cgep7 = getelementptr [64 x i32], ptr %cgep9, i32 0, i32 %and8.i534
    store i32 0, ptr %cgep7, align 4
    %lsr.iv.next = add nsw i32 %lsr.iv, 1
    %cmp157.3 = icmp ult i32 %lsr.iv.next, 510
    br i1 %cmp157.3, label %for.body158, label %for.body170

  for.body170:                                      ; preds = %for.body170, %for.body158
    %lsr.iv3 = phi ptr [ %cgep6, %for.body170 ], [ inttoptr (i32 4 to ptr), %for.body158 ]
    %lsr.iv1 = phi i32 [ %lsr.iv.next2, %for.body170 ], [ -1, %for.body158 ]
    %add11.i556606607 = phi i32 [ 0, %for.body170 ], [ 1, %for.body158 ]
    %cgep5 = getelementptr i8, ptr %lsr.iv3, i32 -4
    store i32 0, ptr %cgep5, align 8
    %sub.i547.1 = add i32 %add11.i556606607, 1
    %and.i548.1 = and i32 %sub.i547.1, 1
    %cgep8 = getelementptr [64 x i32], ptr %cgep9, i32 0, i32 %and.i548.1
    %0 = load i32, ptr %cgep8, align 4
    store i32 %0, ptr %lsr.iv3, align 4
    %lsr.iv.next2 = add nsw i32 %lsr.iv1, 1
    %cmp169.1 = icmp ult i32 %lsr.iv.next2, 254
    %cgep6 = getelementptr i8, ptr %lsr.iv3, i32 2
    br i1 %cmp169.1, label %for.body170, label %for.body147
  }

...
---
name:            test_swp_ws_live_intervals
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_swp_ws_live_intervals
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $r0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:intregs = COPY $r0
  ; CHECK-NEXT:   [[S2_setbit_i:%[0-9]+]]:intregs = S2_setbit_i [[COPY]], 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.5(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.5:
  ; CHECK-NEXT:   successors: %bb.6(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[A2_andir:%[0-9]+]]:intregs = A2_andir [[S2_setbit_i]], 1
  ; CHECK-NEXT:   [[S2_asl_i_r:%[0-9]+]]:intregs = S2_asl_i_r [[A2_andir]], 2
  ; CHECK-NEXT:   [[A2_tfrsi:%[0-9]+]]:intregs = A2_tfrsi 1
  ; CHECK-NEXT:   [[A2_tfrsi1:%[0-9]+]]:intregs = A2_tfrsi 4
  ; CHECK-NEXT:   [[A2_tfrsi2:%[0-9]+]]:intregs = A2_tfrsi 0
  ; CHECK-NEXT:   J2_loop0i %bb.6, 510, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
  ; CHECK-NEXT:   J2_jump %bb.6, implicit-def $pc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.6:
  ; CHECK-NEXT:   successors: %bb.6(0x7c000000), %bb.7(0x04000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:intregs = PHI [[A2_tfrsi2]], %bb.5, %24, %bb.6
  ; CHECK-NEXT:   [[PHI1:%[0-9]+]]:intregs = PHI [[S2_asl_i_r]], %bb.5, %23, %bb.6
  ; CHECK-NEXT:   S4_storeiri_io [[PHI1]], 0, 0 :: (store (s32) into %ir.cgep7)
  ; CHECK-NEXT:   [[A2_andir1:%[0-9]+]]:intregs = A2_andir [[PHI]], 1
  ; CHECK-NEXT:   [[A2_tfrsi3:%[0-9]+]]:intregs = A2_tfrsi 1
  ; CHECK-NEXT:   [[A2_tfrsi4:%[0-9]+]]:intregs = A2_tfrsi 4
  ; CHECK-NEXT:   [[S2_asl_i_r1:%[0-9]+]]:intregs = S2_asl_i_r [[A2_andir1]], 2
  ; CHECK-NEXT:   [[A2_tfrsi5:%[0-9]+]]:intregs = A2_tfrsi 0
  ; CHECK-NEXT:   ENDLOOP0 %bb.6, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
  ; CHECK-NEXT:   J2_jump %bb.7, implicit-def $pc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.7:
  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[PHI2:%[0-9]+]]:intregs = PHI [[S2_asl_i_r1]], %bb.6
  ; CHECK-NEXT:   [[PHI3:%[0-9]+]]:intregs = PHI [[A2_tfrsi3]], %bb.6
  ; CHECK-NEXT:   [[PHI4:%[0-9]+]]:intregs = PHI [[A2_tfrsi4]], %bb.6
  ; CHECK-NEXT:   S4_storeiri_io [[PHI2]], 0, 0 :: (store unknown-size into %ir.cgep7, align 4)
  ; CHECK-NEXT:   J2_jump %bb.3, implicit-def $pc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   J2_loop0i %bb.4, 255, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
  ; CHECK-NEXT:   J2_jump %bb.4, implicit-def $pc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.4:
  ; CHECK-NEXT:   successors: %bb.4(0x7c000000), %bb.1(0x04000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[PHI5:%[0-9]+]]:intregs = PHI [[PHI4]], %bb.3, %9, %bb.4
  ; CHECK-NEXT:   [[PHI6:%[0-9]+]]:intregs = PHI [[PHI3]], %bb.3, %11, %bb.4
  ; CHECK-NEXT:   [[A2_tfrsi6:%[0-9]+]]:intregs = A2_tfrsi 0
  ; CHECK-NEXT:   S2_storeri_io [[PHI5]], -4, [[A2_tfrsi6]] :: (store (s32) into %ir.cgep5, align 8)
  ; CHECK-NEXT:   [[A2_addi:%[0-9]+]]:intregs = A2_addi [[PHI6]], 1
  ; CHECK-NEXT:   [[S2_insert:%[0-9]+]]:intregs = S2_insert [[PHI2]], [[A2_addi]], 1, 2
  ; CHECK-NEXT:   [[L2_loadri_io:%[0-9]+]]:intregs = L2_loadri_io [[S2_insert]], 0 :: (load (s32) from %ir.cgep8)
  ; CHECK-NEXT:   S2_storeri_io [[PHI5]], 0, [[L2_loadri_io]] :: (store (s32) into %ir.lsr.iv3)
  ; CHECK-NEXT:   [[A2_addi1:%[0-9]+]]:intregs = A2_addi [[PHI5]], 2
  ; CHECK-NEXT:   ENDLOOP0 %bb.4, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
  ; CHECK-NEXT:   J2_jump %bb.1, implicit-def dead $pc
  bb.0.entry:
    successors: %bb.1(0x80000000)
    liveins: $r0

    %0:intregs = COPY $r0
    %1:intregs = S2_setbit_i %0, 0

  bb.1:
    successors: %bb.2(0x80000000)

    J2_loop0i %bb.2, 511, implicit-def $lc0, implicit-def $sa0, implicit-def $usr

  bb.2:
    successors: %bb.2(0x7c000000), %bb.3(0x04000000)

    %2:intregs = PHI %1, %bb.1, %3, %bb.2
    %4:intregs = A2_andir %2, 1
    %5:intregs = S2_asl_i_r %4, 2
    S4_storeiri_io %5, 0, 0 :: (store (s32) into %ir.cgep7)
    %6:intregs = A2_tfrsi 1
    %7:intregs = A2_tfrsi 4
    %3:intregs = A2_tfrsi 0
    ENDLOOP0 %bb.2, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
    J2_jump %bb.3, implicit-def dead $pc

  bb.3:
    successors: %bb.4(0x80000000)

    J2_loop0i %bb.4, 255, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
    J2_jump %bb.4, implicit-def $pc

  bb.4:
    successors: %bb.4(0x7c000000), %bb.1(0x04000000)

    %8:intregs = PHI %7, %bb.3, %9, %bb.4
    %10:intregs = PHI %6, %bb.3, %11, %bb.4
    %11:intregs = A2_tfrsi 0
    S2_storeri_io %8, -4, %11 :: (store (s32) into %ir.cgep5, align 8)
    %12:intregs = A2_addi %10, 1
    %13:intregs = S2_insert %5, %12, 1, 2
    %14:intregs = L2_loadri_io %13, 0 :: (load (s32) from %ir.cgep8)
    S2_storeri_io %8, 0, %14 :: (store (s32) into %ir.lsr.iv3)
    %9:intregs = A2_addi %8, 2
    ENDLOOP0 %bb.4, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
    J2_jump %bb.1, implicit-def dead $pc

...