; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s

define <8 x i32> @xvrepl_ins_w(i32 %a, i32 %b) {
; CHECK-LABEL: xvrepl_ins_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvreplgr2vr.w $xr0, $a0
; CHECK-NEXT:    xvinsgr2vr.w $xr0, $a1, 1
; CHECK-NEXT:    ret
entry:
  %0 = call <8 x i32> @llvm.loongarch.lasx.xvreplgr2vr.w(i32 %a)
  %1 = call <8 x i32> @llvm.loongarch.lasx.xvinsgr2vr.w(<8 x i32> %0, i32 %b, i32 1)
  ret <8 x i32> %1
}

declare <8 x i32> @llvm.loongarch.lasx.xvinsgr2vr.w(<8 x i32>, i32, i32 immarg)
declare <8 x i32> @llvm.loongarch.lasx.xvreplgr2vr.w(i32)