; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64

define <64 x i8> @test_i8(<64 x i8> %shuffle) {
; CHECK-LABEL: test_i8:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvrepli.b $xr2, -85
; CHECK-NEXT:    xvmuh.bu $xr0, $xr0, $xr2
; CHECK-NEXT:    xvsrli.b $xr0, $xr0, 1
; CHECK-NEXT:    xvmuh.bu $xr1, $xr1, $xr2
; CHECK-NEXT:    xvsrli.b $xr1, $xr1, 1
; CHECK-NEXT:    ret
entry:
  %div = udiv <64 x i8> %shuffle, splat (i8 3)
  ret <64 x i8> %div
}

define <32 x i16> @test_i16(<32 x i16> %shuffle) {
; CHECK-LABEL: test_i16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lu12i.w $a0, 10
; CHECK-NEXT:    ori $a0, $a0, 2731
; CHECK-NEXT:    xvreplgr2vr.h $xr2, $a0
; CHECK-NEXT:    xvmuh.hu $xr0, $xr0, $xr2
; CHECK-NEXT:    xvsrli.h $xr0, $xr0, 1
; CHECK-NEXT:    xvmuh.hu $xr1, $xr1, $xr2
; CHECK-NEXT:    xvsrli.h $xr1, $xr1, 1
; CHECK-NEXT:    ret
entry:
  %div = udiv <32 x i16> %shuffle, splat (i16 3)
  ret <32 x i16> %div
}

define <16 x i32> @test_i32(<16 x i32> %shuffle) {
; CHECK-LABEL: test_i32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lu12i.w $a0, -349526
; CHECK-NEXT:    ori $a0, $a0, 2731
; CHECK-NEXT:    xvreplgr2vr.w $xr2, $a0
; CHECK-NEXT:    xvmuh.wu $xr0, $xr0, $xr2
; CHECK-NEXT:    xvsrli.w $xr0, $xr0, 1
; CHECK-NEXT:    xvmuh.wu $xr1, $xr1, $xr2
; CHECK-NEXT:    xvsrli.w $xr1, $xr1, 1
; CHECK-NEXT:    ret
entry:
  %div = udiv <16 x i32> %shuffle, splat (i32 3)
  ret <16 x i32> %div
}

define <8 x i64> @test_i64(<8 x i64> %shuffle) {
; LA32-LABEL: test_i64:
; LA32:       # %bb.0: # %entry
; LA32-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI3_0)
; LA32-NEXT:    xvld $xr2, $a0, %pc_lo12(.LCPI3_0)
; LA32-NEXT:    xvmuh.du $xr0, $xr0, $xr2
; LA32-NEXT:    xvsrli.d $xr0, $xr0, 1
; LA32-NEXT:    xvmuh.du $xr1, $xr1, $xr2
; LA32-NEXT:    xvsrli.d $xr1, $xr1, 1
; LA32-NEXT:    ret
;
; LA64-LABEL: test_i64:
; LA64:       # %bb.0: # %entry
; LA64-NEXT:    lu12i.w $a0, -349526
; LA64-NEXT:    ori $a0, $a0, 2731
; LA64-NEXT:    lu32i.d $a0, -349526
; LA64-NEXT:    lu52i.d $a0, $a0, -1366
; LA64-NEXT:    xvreplgr2vr.d $xr2, $a0
; LA64-NEXT:    xvmuh.du $xr0, $xr0, $xr2
; LA64-NEXT:    xvsrli.d $xr0, $xr0, 1
; LA64-NEXT:    xvmuh.du $xr1, $xr1, $xr2
; LA64-NEXT:    xvsrli.d $xr1, $xr1, 1
; LA64-NEXT:    ret
entry:
  %div = udiv <8 x i64> %shuffle, splat (i64 3)
  ret <8 x i64> %div
}

define <64 x i8> @test_sdiv_i8(<64 x i8> %shuffle) {
; CHECK-LABEL: test_sdiv_i8:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvrepli.b $xr2, 86
; CHECK-NEXT:    xvmuh.b $xr0, $xr0, $xr2
; CHECK-NEXT:    xvsrli.b $xr3, $xr0, 7
; CHECK-NEXT:    xvadd.b $xr0, $xr0, $xr3
; CHECK-NEXT:    xvmuh.b $xr1, $xr1, $xr2
; CHECK-NEXT:    xvsrli.b $xr2, $xr1, 7
; CHECK-NEXT:    xvadd.b $xr1, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %div = sdiv <64 x i8> %shuffle, splat (i8 3)
  ret <64 x i8> %div
}