; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64

define void @buildvector_v16i8_splat(ptr %dst, i8 %a0) nounwind {
; CHECK-LABEL: buildvector_v16i8_splat:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vreplgr2vr.b $vr0, $a1
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %insert = insertelement <16 x i8> undef, i8 %a0, i8 0
  %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
  store <16 x i8> %splat, ptr %dst
  ret void
}

define void @buildvector_v8i16_splat(ptr %dst, i16 %a0) nounwind {
; CHECK-LABEL: buildvector_v8i16_splat:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vreplgr2vr.h $vr0, $a1
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %insert = insertelement <8 x i16> undef, i16 %a0, i8 0
  %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
  store <8 x i16> %splat, ptr %dst
  ret void
}

define void @buildvector_v4i32_splat(ptr %dst, i32 %a0) nounwind {
; CHECK-LABEL: buildvector_v4i32_splat:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vreplgr2vr.w $vr0, $a1
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %insert = insertelement <4 x i32> undef, i32 %a0, i8 0
  %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
  store <4 x i32> %splat, ptr %dst
  ret void
}

define void @buildvector_v2i64_splat(ptr %dst, i64 %a0) nounwind {
; LA32-LABEL: buildvector_v2i64_splat:
; LA32:       # %bb.0: # %entry
; LA32-NEXT:    vinsgr2vr.w $vr0, $a1, 0
; LA32-NEXT:    vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT:    vreplvei.d $vr0, $vr0, 0
; LA32-NEXT:    vst $vr0, $a0, 0
; LA32-NEXT:    ret
;
; LA64-LABEL: buildvector_v2i64_splat:
; LA64:       # %bb.0: # %entry
; LA64-NEXT:    vreplgr2vr.d $vr0, $a1
; LA64-NEXT:    vst $vr0, $a0, 0
; LA64-NEXT:    ret
entry:
  %insert = insertelement <2 x i64> undef, i64 %a0, i8 0
  %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
  store <2 x i64> %splat, ptr %dst
  ret void
}

define void @buildvector_v4f32_splat(ptr %dst, float %a0) nounwind {
; CHECK-LABEL: buildvector_v4f32_splat:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    # kill: def $f0 killed $f0 def $vr0
; CHECK-NEXT:    vreplvei.w $vr0, $vr0, 0
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %insert = insertelement <4 x float> undef, float %a0, i8 0
  %splat = shufflevector <4 x float> %insert, <4 x float> undef, <4 x i32> zeroinitializer
  store <4 x float> %splat, ptr %dst
  ret void
}

define void @buildvector_v2f64_splat(ptr %dst, double %a0) nounwind {
; CHECK-LABEL: buildvector_v2f64_splat:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    # kill: def $f0_64 killed $f0_64 def $vr0
; CHECK-NEXT:    vreplvei.d $vr0, $vr0, 0
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %insert = insertelement <2 x double> undef, double %a0, i8 0
  %splat = shufflevector <2 x double> %insert, <2 x double> undef, <2 x i32> zeroinitializer
  store <2 x double> %splat, ptr %dst
  ret void
}

define void @buildvector_v16i8_const_splat(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v16i8_const_splat:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vrepli.b $vr0, 1
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  store <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, ptr %dst
  ret void
}

define void @buildvector_v16i8_const_splat_v2i64(ptr %dst) nounwind {
; LA32-LABEL: buildvector_v16i8_const_splat_v2i64:
; LA32:       # %bb.0: # %entry
; LA32-NEXT:    pcalau12i $a1, %pc_hi20(.LCPI7_0)
; LA32-NEXT:    vld $vr0, $a1, %pc_lo12(.LCPI7_0)
; LA32-NEXT:    vst $vr0, $a0, 0
; LA32-NEXT:    ret
;
; LA64-LABEL: buildvector_v16i8_const_splat_v2i64:
; LA64:       # %bb.0: # %entry
; LA64-NEXT:    lu12i.w $a1, 7
; LA64-NEXT:    ori $a1, $a1, 3453
; LA64-NEXT:    vreplgr2vr.d $vr0, $a1
; LA64-NEXT:    vst $vr0, $a0, 0
; LA64-NEXT:    ret
entry:
  store <16 x i8> <i8 125, i8 125, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 125, i8 125, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, ptr %dst
  ret void
}

define void @buildvector_v8i16_const_splat(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v8i16_const_splat:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vrepli.h $vr0, 1
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  store <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, ptr %dst
  ret void
}

define void @buildvector_v8i16_const_splat_v2i64(ptr %dst) nounwind {
; LA32-LABEL: buildvector_v8i16_const_splat_v2i64:
; LA32:       # %bb.0: # %entry
; LA32-NEXT:    pcalau12i $a1, %pc_hi20(.LCPI9_0)
; LA32-NEXT:    vld $vr0, $a1, %pc_lo12(.LCPI9_0)
; LA32-NEXT:    vst $vr0, $a0, 0
; LA32-NEXT:    ret
;
; LA64-LABEL: buildvector_v8i16_const_splat_v2i64:
; LA64:       # %bb.0: # %entry
; LA64-NEXT:    ori $a1, $zero, 512
; LA64-NEXT:    vreplgr2vr.d $vr0, $a1
; LA64-NEXT:    vst $vr0, $a0, 0
; LA64-NEXT:    ret
entry:
  store <8 x i16> <i16 512, i16 0, i16 0, i16 0, i16 512, i16 0, i16 0, i16 0>, ptr %dst
  ret void
}

define void @buildvector_v4i32_const_splat(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v4i32_const_splat:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vrepli.w $vr0, 1
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, ptr %dst
  ret void
}

define void @buildvector_v4i32_const_splat_v2i64(ptr %dst) nounwind {
; LA32-LABEL: buildvector_v4i32_const_splat_v2i64:
; LA32:       # %bb.0: # %entry
; LA32-NEXT:    pcalau12i $a1, %pc_hi20(.LCPI11_0)
; LA32-NEXT:    vld $vr0, $a1, %pc_lo12(.LCPI11_0)
; LA32-NEXT:    vst $vr0, $a0, 0
; LA32-NEXT:    ret
;
; LA64-LABEL: buildvector_v4i32_const_splat_v2i64:
; LA64:       # %bb.0: # %entry
; LA64-NEXT:    ori $a1, $zero, 512
; LA64-NEXT:    vreplgr2vr.d $vr0, $a1
; LA64-NEXT:    vst $vr0, $a0, 0
; LA64-NEXT:    ret
entry:
  store <4 x i32> <i32 512, i32 0, i32 512, i32 0>, ptr %dst
  ret void
}

define void @buildvector_v2i64_const_splat(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v2i64_const_splat:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vrepli.d $vr0, 1
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  store <2 x i64> <i64 1, i64 1>, ptr %dst
  ret void
}

;; Also check buildvector_const_splat_vldi_1010.
define void @buildvector_v4f32_const_splat(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v4f32_const_splat:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vldi $vr0, -1424
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  store <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, ptr %dst
  ret void
}

;; Also check buildvector_const_splat_vldi_1100.
define void @buildvector_v2f64_const_splat(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v2f64_const_splat:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vldi $vr0, -912
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  store <2 x double> <double 1.0, double 1.0>, ptr %dst
  ret void
}

;; imm[11:8] == 4'b0000/4'b0100/4'b1000 can be represented using vrepli.[whb].
define void @buildvector_const_splat_vldi_0001(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_const_splat_vldi_0001:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vldi $vr0, -3837
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  store <4 x i32> <i32 768, i32 768, i32 768, i32 768>, ptr %dst
  ret void
}

define void @buildvector_const_splat_vldi_0010(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_const_splat_vldi_0010:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vldi $vr0, -3583
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  store <4 x i32> <i32 65536, i32 65536, i32 65536, i32 65536>, ptr %dst
  ret void
}

define void @buildvector_const_splat_vldi_0011(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_const_splat_vldi_0011:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vldi $vr0, -3327
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  store <4 x i32> <i32 16777216, i32 16777216, i32 16777216, i32 16777216>, ptr %dst
  ret void
}

define void @buildvector_const_splat_vldi_0101(ptr %dst) {
; CHECK-LABEL: buildvector_const_splat_vldi_0101:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vldi $vr0, -2813
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  store <8 x i16> <i16 768, i16 768, i16 768, i16 768, i16 768, i16 768, i16 768, i16 768>, ptr %dst
  ret void
}

define void @buildvector_const_splat_vldi_0110(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_const_splat_vldi_0110:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vldi $vr0, -2557
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  store <4 x i32> <i32 1023, i32 1023, i32 1023, i32 1023>, ptr %dst
  ret void
}

define void @buildvector_const_splat_vldi_0111(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_const_splat_vldi_0111:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vldi $vr0, -2305
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  store <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>, ptr %dst
  ret void
}

define void @buildvector_const_splat_vldi_1001(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_const_splat_vldi_1001:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vldi $vr0, -1789
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  store <4 x i32> <i32 65535, i32 0, i32 65535, i32 0>, ptr %dst
  ret void
}

define void @buildvector_const_splat_vldi_1011(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_const_splat_vldi_1011:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vldi $vr0, -1280
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  store <4 x float> <float 2.0, float 0.0, float 2.0, float 0.0>, ptr %dst
  ret void
}

define void @buildvector_v16i8_const(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v16i8_const:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    pcalau12i $a1, %pc_hi20(.LCPI23_0)
; CHECK-NEXT:    vld $vr0, $a1, %pc_lo12(.LCPI23_0)
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  store <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, ptr %dst
  ret void
}

define void @buildvector_v8i16_const(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v8i16_const:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    pcalau12i $a1, %pc_hi20(.LCPI24_0)
; CHECK-NEXT:    vld $vr0, $a1, %pc_lo12(.LCPI24_0)
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  store <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, ptr %dst
  ret void
}

define void @buildvector_v4i32_const(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v4i32_const:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    pcalau12i $a1, %pc_hi20(.LCPI25_0)
; CHECK-NEXT:    vld $vr0, $a1, %pc_lo12(.LCPI25_0)
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, ptr %dst
  ret void
}

define void @buildvector_v2i64_const(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v2i64_const:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    pcalau12i $a1, %pc_hi20(.LCPI26_0)
; CHECK-NEXT:    vld $vr0, $a1, %pc_lo12(.LCPI26_0)
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  store <2 x i64> <i64 0, i64 1>, ptr %dst
  ret void
}

define void @buildvector_v2f32_const(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v2f32_const:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    pcalau12i $a1, %pc_hi20(.LCPI27_0)
; CHECK-NEXT:    vld $vr0, $a1, %pc_lo12(.LCPI27_0)
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  store <4 x float> <float 0.0, float 1.0, float 2.0, float 3.0>, ptr %dst
  ret void
}

define void @buildvector_v2f64_const(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v2f64_const:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    pcalau12i $a1, %pc_hi20(.LCPI28_0)
; CHECK-NEXT:    vld $vr0, $a1, %pc_lo12(.LCPI28_0)
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  store <2 x double> <double 0.0, double 1.0>, ptr %dst
  ret void
}

define void @buildvector_v16i8(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15) nounwind {
; LA32-LABEL: buildvector_v16i8:
; LA32:       # %bb.0: # %entry
; LA32-NEXT:    ld.b $t0, $sp, 32
; LA32-NEXT:    ld.b $t1, $sp, 28
; LA32-NEXT:    ld.b $t2, $sp, 24
; LA32-NEXT:    ld.b $t3, $sp, 20
; LA32-NEXT:    ld.b $t4, $sp, 16
; LA32-NEXT:    ld.b $t5, $sp, 12
; LA32-NEXT:    ld.b $t6, $sp, 8
; LA32-NEXT:    ld.b $t7, $sp, 4
; LA32-NEXT:    ld.b $t8, $sp, 0
; LA32-NEXT:    vinsgr2vr.b $vr0, $a1, 0
; LA32-NEXT:    vinsgr2vr.b $vr0, $a2, 1
; LA32-NEXT:    vinsgr2vr.b $vr0, $a3, 2
; LA32-NEXT:    vinsgr2vr.b $vr0, $a4, 3
; LA32-NEXT:    vinsgr2vr.b $vr0, $a5, 4
; LA32-NEXT:    vinsgr2vr.b $vr0, $a6, 5
; LA32-NEXT:    vinsgr2vr.b $vr0, $a7, 6
; LA32-NEXT:    vinsgr2vr.b $vr0, $t8, 7
; LA32-NEXT:    vinsgr2vr.b $vr0, $t7, 8
; LA32-NEXT:    vinsgr2vr.b $vr0, $t6, 9
; LA32-NEXT:    vinsgr2vr.b $vr0, $t5, 10
; LA32-NEXT:    vinsgr2vr.b $vr0, $t4, 11
; LA32-NEXT:    vinsgr2vr.b $vr0, $t3, 12
; LA32-NEXT:    vinsgr2vr.b $vr0, $t2, 13
; LA32-NEXT:    vinsgr2vr.b $vr0, $t1, 14
; LA32-NEXT:    vinsgr2vr.b $vr0, $t0, 15
; LA32-NEXT:    vst $vr0, $a0, 0
; LA32-NEXT:    ret
;
; LA64-LABEL: buildvector_v16i8:
; LA64:       # %bb.0: # %entry
; LA64-NEXT:    ld.b $t0, $sp, 64
; LA64-NEXT:    ld.b $t1, $sp, 56
; LA64-NEXT:    ld.b $t2, $sp, 48
; LA64-NEXT:    ld.b $t3, $sp, 40
; LA64-NEXT:    ld.b $t4, $sp, 32
; LA64-NEXT:    ld.b $t5, $sp, 24
; LA64-NEXT:    ld.b $t6, $sp, 16
; LA64-NEXT:    ld.b $t7, $sp, 8
; LA64-NEXT:    ld.b $t8, $sp, 0
; LA64-NEXT:    vinsgr2vr.b $vr0, $a1, 0
; LA64-NEXT:    vinsgr2vr.b $vr0, $a2, 1
; LA64-NEXT:    vinsgr2vr.b $vr0, $a3, 2
; LA64-NEXT:    vinsgr2vr.b $vr0, $a4, 3
; LA64-NEXT:    vinsgr2vr.b $vr0, $a5, 4
; LA64-NEXT:    vinsgr2vr.b $vr0, $a6, 5
; LA64-NEXT:    vinsgr2vr.b $vr0, $a7, 6
; LA64-NEXT:    vinsgr2vr.b $vr0, $t8, 7
; LA64-NEXT:    vinsgr2vr.b $vr0, $t7, 8
; LA64-NEXT:    vinsgr2vr.b $vr0, $t6, 9
; LA64-NEXT:    vinsgr2vr.b $vr0, $t5, 10
; LA64-NEXT:    vinsgr2vr.b $vr0, $t4, 11
; LA64-NEXT:    vinsgr2vr.b $vr0, $t3, 12
; LA64-NEXT:    vinsgr2vr.b $vr0, $t2, 13
; LA64-NEXT:    vinsgr2vr.b $vr0, $t1, 14
; LA64-NEXT:    vinsgr2vr.b $vr0, $t0, 15
; LA64-NEXT:    vst $vr0, $a0, 0
; LA64-NEXT:    ret
entry:
  %ins0  = insertelement <16 x i8> undef,  i8 %a0,  i32 0
  %ins1  = insertelement <16 x i8> %ins0,  i8 %a1,  i32 1
  %ins2  = insertelement <16 x i8> %ins1,  i8 %a2,  i32 2
  %ins3  = insertelement <16 x i8> %ins2,  i8 %a3,  i32 3
  %ins4  = insertelement <16 x i8> %ins3,  i8 %a4,  i32 4
  %ins5  = insertelement <16 x i8> %ins4,  i8 %a5,  i32 5
  %ins6  = insertelement <16 x i8> %ins5,  i8 %a6,  i32 6
  %ins7  = insertelement <16 x i8> %ins6,  i8 %a7,  i32 7
  %ins8  = insertelement <16 x i8> %ins7,  i8 %a8,  i32 8
  %ins9  = insertelement <16 x i8> %ins8,  i8 %a9,  i32 9
  %ins10 = insertelement <16 x i8> %ins9,  i8 %a10, i32 10
  %ins11 = insertelement <16 x i8> %ins10, i8 %a11, i32 11
  %ins12 = insertelement <16 x i8> %ins11, i8 %a12, i32 12
  %ins13 = insertelement <16 x i8> %ins12, i8 %a13, i32 13
  %ins14 = insertelement <16 x i8> %ins13, i8 %a14, i32 14
  %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15
  store <16 x i8> %ins15, ptr %dst
  ret void
}

define void @buildvector_v16i8_partial(ptr %dst, i8 %a2, i8 %a6, i8 %a8, i8 %a11, i8 %a12, i8 %a15) nounwind {
; CHECK-LABEL: buildvector_v16i8_partial:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a1, 2
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a2, 6
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a3, 8
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a4, 11
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a5, 12
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a6, 15
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0  = insertelement <16 x i8> undef,  i8 undef, i32 0
  %ins1  = insertelement <16 x i8> %ins0,  i8 undef, i32 1
  %ins2  = insertelement <16 x i8> %ins1,  i8   %a2, i32 2
  %ins3  = insertelement <16 x i8> %ins2,  i8 undef, i32 3
  %ins4  = insertelement <16 x i8> %ins3,  i8 undef, i32 4
  %ins5  = insertelement <16 x i8> %ins4,  i8 undef, i32 5
  %ins6  = insertelement <16 x i8> %ins5,  i8   %a6, i32 6
  %ins7  = insertelement <16 x i8> %ins6,  i8 undef, i32 7
  %ins8  = insertelement <16 x i8> %ins7,  i8   %a8, i32 8
  %ins9  = insertelement <16 x i8> %ins8,  i8 undef, i32 9
  %ins10 = insertelement <16 x i8> %ins9,  i8 undef, i32 10
  %ins11 = insertelement <16 x i8> %ins10, i8  %a11, i32 11
  %ins12 = insertelement <16 x i8> %ins11, i8  %a12, i32 12
  %ins13 = insertelement <16 x i8> %ins12, i8 undef, i32 13
  %ins14 = insertelement <16 x i8> %ins13, i8 undef, i32 14
  %ins15 = insertelement <16 x i8> %ins14, i8  %a15, i32 15
  store <16 x i8> %ins15, ptr %dst
  ret void
}

define void @buildvector_v16i8_with_constant(ptr %dst, i8 %a0, i8 %a4, i8 %a6, i8 %a8, i8 %a11, i8 %a12, i8 %a15) nounwind {
; CHECK-LABEL: buildvector_v16i8_with_constant:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vrepli.b $vr0, 0
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a1, 0
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a2, 4
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a3, 6
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a4, 8
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a5, 11
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a6, 12
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a7, 15
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0  = insertelement <16 x i8> undef,  i8  %a0, i32 0
  %ins1  = insertelement <16 x i8> %ins0,  i8    0, i32 1
  %ins2  = insertelement <16 x i8> %ins1,  i8    0, i32 2
  %ins3  = insertelement <16 x i8> %ins2,  i8    0, i32 3
  %ins4  = insertelement <16 x i8> %ins3,  i8  %a4, i32 4
  %ins5  = insertelement <16 x i8> %ins4,  i8    0, i32 5
  %ins6  = insertelement <16 x i8> %ins5,  i8  %a6, i32 6
  %ins7  = insertelement <16 x i8> %ins6,  i8    0, i32 7
  %ins8  = insertelement <16 x i8> %ins7,  i8  %a8, i32 8
  %ins9  = insertelement <16 x i8> %ins8,  i8    0, i32 9
  %ins10 = insertelement <16 x i8> %ins9,  i8    0, i32 10
  %ins11 = insertelement <16 x i8> %ins10, i8 %a11, i32 11
  %ins12 = insertelement <16 x i8> %ins11, i8 %a12, i32 12
  %ins13 = insertelement <16 x i8> %ins12, i8    0, i32 13
  %ins14 = insertelement <16 x i8> %ins13, i8    0, i32 14
  %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15
  store <16 x i8> %ins15, ptr %dst
  ret void
}

define void @buildvector_v16i8_subseq_2(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7) nounwind {
; CHECK-LABEL: buildvector_v16i8_subseq_2:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    ld.b $t0, $sp, 0
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a1, 0
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a2, 1
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a3, 2
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a4, 3
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a5, 4
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a6, 5
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a7, 6
; CHECK-NEXT:    vinsgr2vr.b $vr0, $t0, 7
; CHECK-NEXT:    vreplvei.d $vr0, $vr0, 0
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0  = insertelement <16 x i8> undef,  i8 %a0, i32 0
  %ins1  = insertelement <16 x i8> %ins0,  i8 %a1, i32 1
  %ins2  = insertelement <16 x i8> %ins1,  i8 %a2, i32 2
  %ins3  = insertelement <16 x i8> %ins2,  i8 %a3, i32 3
  %ins4  = insertelement <16 x i8> %ins3,  i8 %a4, i32 4
  %ins5  = insertelement <16 x i8> %ins4,  i8 %a5, i32 5
  %ins6  = insertelement <16 x i8> %ins5,  i8 %a6, i32 6
  %ins7  = insertelement <16 x i8> %ins6,  i8 %a7, i32 7
  %ins8  = insertelement <16 x i8> %ins7,  i8 %a0, i32 8
  %ins9  = insertelement <16 x i8> %ins8,  i8 %a1, i32 9
  %ins10 = insertelement <16 x i8> %ins9,  i8 %a2, i32 10
  %ins11 = insertelement <16 x i8> %ins10, i8 %a3, i32 11
  %ins12 = insertelement <16 x i8> %ins11, i8 %a4, i32 12
  %ins13 = insertelement <16 x i8> %ins12, i8 %a5, i32 13
  %ins14 = insertelement <16 x i8> %ins13, i8 %a6, i32 14
  %ins15 = insertelement <16 x i8> %ins14, i8 %a7, i32 15
  store <16 x i8> %ins15, ptr %dst
  ret void
}

define void @buildvector_v16i8_subseq_4(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3) nounwind {
; CHECK-LABEL: buildvector_v16i8_subseq_4:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a1, 0
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a2, 1
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a3, 2
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a4, 3
; CHECK-NEXT:    vreplvei.w $vr0, $vr0, 0
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0  = insertelement <16 x i8> undef,  i8 %a0, i32 0
  %ins1  = insertelement <16 x i8> %ins0,  i8 %a1, i32 1
  %ins2  = insertelement <16 x i8> %ins1,  i8 %a2, i32 2
  %ins3  = insertelement <16 x i8> %ins2,  i8 %a3, i32 3
  %ins4  = insertelement <16 x i8> %ins3,  i8 %a0, i32 4
  %ins5  = insertelement <16 x i8> %ins4,  i8 %a1, i32 5
  %ins6  = insertelement <16 x i8> %ins5,  i8 %a2, i32 6
  %ins7  = insertelement <16 x i8> %ins6,  i8 %a3, i32 7
  %ins8  = insertelement <16 x i8> %ins7,  i8 %a0, i32 8
  %ins9  = insertelement <16 x i8> %ins8,  i8 %a1, i32 9
  %ins10 = insertelement <16 x i8> %ins9,  i8 %a2, i32 10
  %ins11 = insertelement <16 x i8> %ins10, i8 %a3, i32 11
  %ins12 = insertelement <16 x i8> %ins11, i8 %a0, i32 12
  %ins13 = insertelement <16 x i8> %ins12, i8 %a1, i32 13
  %ins14 = insertelement <16 x i8> %ins13, i8 %a2, i32 14
  %ins15 = insertelement <16 x i8> %ins14, i8 %a3, i32 15
  store <16 x i8> %ins15, ptr %dst
  ret void
}

define void @buildvector_v16i8_subseq_8(ptr %dst, i8 %a0, i8 %a1) nounwind {
; CHECK-LABEL: buildvector_v16i8_subseq_8:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a1, 0
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a2, 1
; CHECK-NEXT:    vreplvei.h $vr0, $vr0, 0
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0  = insertelement <16 x i8> undef,  i8 %a0, i32 0
  %ins1  = insertelement <16 x i8> %ins0,  i8 %a1, i32 1
  %ins2  = insertelement <16 x i8> %ins1,  i8 %a0, i32 2
  %ins3  = insertelement <16 x i8> %ins2,  i8 %a1, i32 3
  %ins4  = insertelement <16 x i8> %ins3,  i8 %a0, i32 4
  %ins5  = insertelement <16 x i8> %ins4,  i8 %a1, i32 5
  %ins6  = insertelement <16 x i8> %ins5,  i8 %a0, i32 6
  %ins7  = insertelement <16 x i8> %ins6,  i8 %a1, i32 7
  %ins8  = insertelement <16 x i8> %ins7,  i8 %a0, i32 8
  %ins9  = insertelement <16 x i8> %ins8,  i8 %a1, i32 9
  %ins10 = insertelement <16 x i8> %ins9,  i8 %a0, i32 10
  %ins11 = insertelement <16 x i8> %ins10, i8 %a1, i32 11
  %ins12 = insertelement <16 x i8> %ins11, i8 %a0, i32 12
  %ins13 = insertelement <16 x i8> %ins12, i8 %a1, i32 13
  %ins14 = insertelement <16 x i8> %ins13, i8 %a0, i32 14
  %ins15 = insertelement <16 x i8> %ins14, i8 %a1, i32 15
  store <16 x i8> %ins15, ptr %dst
  ret void
}

define void @buildvector_v8i16(ptr %dst, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind {
; CHECK-LABEL: buildvector_v8i16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    ld.h $t0, $sp, 0
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a1, 0
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a2, 1
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a3, 2
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a4, 3
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a5, 4
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a6, 5
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a7, 6
; CHECK-NEXT:    vinsgr2vr.h $vr0, $t0, 7
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0
  %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1
  %ins2 = insertelement <8 x i16> %ins1, i16 %a2, i32 2
  %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3
  %ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4
  %ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5
  %ins6 = insertelement <8 x i16> %ins5, i16 %a6, i32 6
  %ins7 = insertelement <8 x i16> %ins6, i16 %a7, i32 7
  store <8 x i16> %ins7, ptr %dst
  ret void
}

define void @buildvector_v8i16_partial(ptr %dst, i16 %a1, i16 %a3, i16 %a4, i16 %a5) nounwind {
; CHECK-LABEL: buildvector_v8i16_partial:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a1, 1
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a2, 3
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a3, 4
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a4, 5
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0 = insertelement <8 x i16> undef, i16 undef, i32 0
  %ins1 = insertelement <8 x i16> %ins0, i16   %a1, i32 1
  %ins2 = insertelement <8 x i16> %ins1, i16 undef, i32 2
  %ins3 = insertelement <8 x i16> %ins2, i16   %a3, i32 3
  %ins4 = insertelement <8 x i16> %ins3, i16   %a4, i32 4
  %ins5 = insertelement <8 x i16> %ins4, i16   %a5, i32 5
  %ins6 = insertelement <8 x i16> %ins5, i16 undef, i32 6
  %ins7 = insertelement <8 x i16> %ins6, i16 undef, i32 7
  store <8 x i16> %ins7, ptr %dst
  ret void
}

define void @buildvector_v8i16_with_constant(ptr %dst, i16 %a0, i16 %a3, i16 %a4, i16 %a5) nounwind {
; CHECK-LABEL: buildvector_v8i16_with_constant:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vrepli.b $vr0, 0
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a1, 0
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a2, 3
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a3, 4
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a4, 5
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0 = insertelement <8 x i16> undef, i16   %a0, i32 0
  %ins1 = insertelement <8 x i16> %ins0, i16     0, i32 1
  %ins2 = insertelement <8 x i16> %ins1, i16 undef, i32 2
  %ins3 = insertelement <8 x i16> %ins2, i16   %a3, i32 3
  %ins4 = insertelement <8 x i16> %ins3, i16   %a4, i32 4
  %ins5 = insertelement <8 x i16> %ins4, i16   %a5, i32 5
  %ins6 = insertelement <8 x i16> %ins5, i16     0, i32 6
  %ins7 = insertelement <8 x i16> %ins6, i16 undef, i32 7
  store <8 x i16> %ins7, ptr %dst
  ret void
}

define void @buildvector_v8i16_subseq_2(ptr %dst, i16 %a0, i16 %a1, i16 %a2, i16 %a3) nounwind {
; CHECK-LABEL: buildvector_v8i16_subseq_2:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a1, 0
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a2, 1
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a3, 2
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a4, 3
; CHECK-NEXT:    vreplvei.d $vr0, $vr0, 0
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0
  %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1
  %ins2 = insertelement <8 x i16> %ins1, i16 %a2, i32 2
  %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3
  %ins4 = insertelement <8 x i16> %ins3, i16 %a0, i32 4
  %ins5 = insertelement <8 x i16> %ins4, i16 %a1, i32 5
  %ins6 = insertelement <8 x i16> %ins5, i16 %a2, i32 6
  %ins7 = insertelement <8 x i16> %ins6, i16 %a3, i32 7
  store <8 x i16> %ins7, ptr %dst
  ret void
}

define void @buildvector_v8i16_subseq_4(ptr %dst, i16 %a0, i16 %a1) nounwind {
; CHECK-LABEL: buildvector_v8i16_subseq_4:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a1, 0
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a2, 1
; CHECK-NEXT:    vreplvei.w $vr0, $vr0, 0
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0
  %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1
  %ins2 = insertelement <8 x i16> %ins1, i16 %a0, i32 2
  %ins3 = insertelement <8 x i16> %ins2, i16 %a1, i32 3
  %ins4 = insertelement <8 x i16> %ins3, i16 %a0, i32 4
  %ins5 = insertelement <8 x i16> %ins4, i16 %a1, i32 5
  %ins6 = insertelement <8 x i16> %ins5, i16 %a0, i32 6
  %ins7 = insertelement <8 x i16> %ins6, i16 %a1, i32 7
  store <8 x i16> %ins7, ptr %dst
  ret void
}

define void @buildvector_v4i32(ptr %dst, i32 %a0, i32 %a1, i32 %a2, i32 %a3) nounwind {
; CHECK-LABEL: buildvector_v4i32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vinsgr2vr.w $vr0, $a1, 0
; CHECK-NEXT:    vinsgr2vr.w $vr0, $a2, 1
; CHECK-NEXT:    vinsgr2vr.w $vr0, $a3, 2
; CHECK-NEXT:    vinsgr2vr.w $vr0, $a4, 3
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0
  %ins1 = insertelement <4 x i32> %ins0, i32 %a1, i32 1
  %ins2 = insertelement <4 x i32> %ins1, i32 %a2, i32 2
  %ins3 = insertelement <4 x i32> %ins2, i32 %a3, i32 3
  store <4 x i32> %ins3, ptr %dst
  ret void
}

define void @buildvector_v4i32_partial(ptr %dst, i32 %a0, i32 %a3) nounwind {
; CHECK-LABEL: buildvector_v4i32_partial:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vinsgr2vr.w $vr0, $a1, 0
; CHECK-NEXT:    vinsgr2vr.w $vr0, $a2, 3
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0 = insertelement <4 x i32> undef, i32   %a0, i32 0
  %ins1 = insertelement <4 x i32> %ins0, i32 undef, i32 1
  %ins2 = insertelement <4 x i32> %ins1, i32 undef, i32 2
  %ins3 = insertelement <4 x i32> %ins2, i32   %a3, i32 3
  store <4 x i32> %ins3, ptr %dst
  ret void
}

define void @buildvector_v4i32_with_constant(ptr %dst, i32 %a0, i32 %a2, i32 %a3) nounwind {
; CHECK-LABEL: buildvector_v4i32_with_constant:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vrepli.w $vr0, 2
; CHECK-NEXT:    vinsgr2vr.w $vr0, $a1, 0
; CHECK-NEXT:    vinsgr2vr.w $vr0, $a2, 2
; CHECK-NEXT:    vinsgr2vr.w $vr0, $a3, 3
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0
  %ins1 = insertelement <4 x i32> %ins0, i32   2, i32 1
  %ins2 = insertelement <4 x i32> %ins1, i32 %a2, i32 2
  %ins3 = insertelement <4 x i32> %ins2, i32 %a3, i32 3
  store <4 x i32> %ins3, ptr %dst
  ret void
}

define void @buildvector_v4i32_subseq_2(ptr %dst, i32 %a0, i32 %a1) nounwind {
; CHECK-LABEL: buildvector_v4i32_subseq_2:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vinsgr2vr.w $vr0, $a1, 0
; CHECK-NEXT:    vinsgr2vr.w $vr0, $a2, 1
; CHECK-NEXT:    vreplvei.d $vr0, $vr0, 0
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0
  %ins1 = insertelement <4 x i32> %ins0, i32 %a1, i32 1
  %ins2 = insertelement <4 x i32> %ins1, i32 %a0, i32 2
  %ins3 = insertelement <4 x i32> %ins2, i32 %a1, i32 3
  store <4 x i32> %ins3, ptr %dst
  ret void
}

define void @buildvector_v2i64(ptr %dst, i64 %a0, i64 %a1) nounwind {
; LA32-LABEL: buildvector_v2i64:
; LA32:       # %bb.0: # %entry
; LA32-NEXT:    vinsgr2vr.w $vr0, $a1, 0
; LA32-NEXT:    vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT:    vinsgr2vr.w $vr0, $a3, 2
; LA32-NEXT:    vinsgr2vr.w $vr0, $a4, 3
; LA32-NEXT:    vst $vr0, $a0, 0
; LA32-NEXT:    ret
;
; LA64-LABEL: buildvector_v2i64:
; LA64:       # %bb.0: # %entry
; LA64-NEXT:    vinsgr2vr.d $vr0, $a1, 0
; LA64-NEXT:    vinsgr2vr.d $vr0, $a2, 1
; LA64-NEXT:    vst $vr0, $a0, 0
; LA64-NEXT:    ret
entry:
  %ins0 = insertelement <2 x i64> undef, i64 %a0, i32 0
  %ins1 = insertelement <2 x i64> %ins0, i64 %a1, i32 1
  store <2 x i64> %ins1, ptr %dst
  ret void
}

define void @buildvector_v2i64_partial(ptr %dst, i64 %a0) nounwind {
; LA32-LABEL: buildvector_v2i64_partial:
; LA32:       # %bb.0: # %entry
; LA32-NEXT:    vinsgr2vr.w $vr0, $a1, 0
; LA32-NEXT:    vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT:    vst $vr0, $a0, 0
; LA32-NEXT:    ret
;
; LA64-LABEL: buildvector_v2i64_partial:
; LA64:       # %bb.0: # %entry
; LA64-NEXT:    vinsgr2vr.d $vr0, $a1, 0
; LA64-NEXT:    vst $vr0, $a0, 0
; LA64-NEXT:    ret
entry:
  %ins0 = insertelement <2 x i64> undef, i64   %a0, i32 0
  %ins1 = insertelement <2 x i64> %ins0, i64 undef, i32 1
  store <2 x i64> %ins1, ptr %dst
  ret void
}

define void @buildvector_v2i64_with_constant(ptr %dst, i64 %a1) nounwind {
; LA32-LABEL: buildvector_v2i64_with_constant:
; LA32:       # %bb.0: # %entry
; LA32-NEXT:    vrepli.b $vr0, 0
; LA32-NEXT:    vinsgr2vr.w $vr0, $a1, 2
; LA32-NEXT:    vinsgr2vr.w $vr0, $a2, 3
; LA32-NEXT:    vst $vr0, $a0, 0
; LA32-NEXT:    ret
;
; LA64-LABEL: buildvector_v2i64_with_constant:
; LA64:       # %bb.0: # %entry
; LA64-NEXT:    vrepli.b $vr0, 0
; LA64-NEXT:    vinsgr2vr.d $vr0, $a1, 1
; LA64-NEXT:    vst $vr0, $a0, 0
; LA64-NEXT:    ret
entry:
  %ins0 = insertelement <2 x i64> undef, i64   0, i32 0
  %ins1 = insertelement <2 x i64> %ins0, i64 %a1, i32 1
  store <2 x i64> %ins1, ptr %dst
  ret void
}

define void @buildvector_v4f32(ptr %dst, float %a0, float %a1, float %a2, float %a3) nounwind {
; CHECK-LABEL: buildvector_v4f32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    # kill: def $f3 killed $f3 def $vr3
; CHECK-NEXT:    # kill: def $f2 killed $f2 def $vr2
; CHECK-NEXT:    # kill: def $f1 killed $f1 def $vr1
; CHECK-NEXT:    # kill: def $f0 killed $f0 def $vr0
; CHECK-NEXT:    vextrins.w $vr0, $vr1, 16
; CHECK-NEXT:    vextrins.w $vr0, $vr2, 32
; CHECK-NEXT:    vextrins.w $vr0, $vr3, 48
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0 = insertelement <4 x float> undef, float %a0, i32 0
  %ins1 = insertelement <4 x float> %ins0, float %a1, i32 1
  %ins2 = insertelement <4 x float> %ins1, float %a2, i32 2
  %ins3 = insertelement <4 x float> %ins2, float %a3, i32 3
  store <4 x float> %ins3, ptr %dst
  ret void
}

define void @buildvector_v4f32_partial(ptr %dst, float %a0, float %a3) nounwind {
; CHECK-LABEL: buildvector_v4f32_partial:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    # kill: def $f1 killed $f1 def $vr1
; CHECK-NEXT:    # kill: def $f0 killed $f0 def $vr0
; CHECK-NEXT:    vextrins.w $vr0, $vr1, 48
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0 = insertelement <4 x float> undef, float   %a0, i32 0
  %ins1 = insertelement <4 x float> %ins0, float undef, i32 1
  %ins2 = insertelement <4 x float> %ins1, float undef, i32 2
  %ins3 = insertelement <4 x float> %ins2, float   %a3, i32 3
  store <4 x float> %ins3, ptr %dst
  ret void
}

define void @buildvector_v4f32_with_constant(ptr %dst, float %a1, float %a2, float %a3) nounwind {
; CHECK-LABEL: buildvector_v4f32_with_constant:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    # kill: def $f2 killed $f2 def $vr2
; CHECK-NEXT:    # kill: def $f1 killed $f1 def $vr1
; CHECK-NEXT:    # kill: def $f0 killed $f0 def $vr0
; CHECK-NEXT:    vrepli.b $vr3, 0
; CHECK-NEXT:    vextrins.w $vr3, $vr0, 16
; CHECK-NEXT:    vextrins.w $vr3, $vr1, 32
; CHECK-NEXT:    vextrins.w $vr3, $vr2, 48
; CHECK-NEXT:    vst $vr3, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0 = insertelement <4 x float> undef, float 0.0, i32 0
  %ins1 = insertelement <4 x float> %ins0, float %a1, i32 1
  %ins2 = insertelement <4 x float> %ins1, float %a2, i32 2
  %ins3 = insertelement <4 x float> %ins2, float %a3, i32 3
  store <4 x float> %ins3, ptr %dst
  ret void
}

define void @buildvector_v4f32_subseq_2(ptr %dst, float %a0, float %a1) nounwind {
; CHECK-LABEL: buildvector_v4f32_subseq_2:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    # kill: def $f1 killed $f1 def $vr1
; CHECK-NEXT:    # kill: def $f0 killed $f0 def $vr0
; CHECK-NEXT:    vextrins.w $vr0, $vr1, 16
; CHECK-NEXT:    vreplvei.d $vr0, $vr0, 0
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0 = insertelement <4 x float> undef, float %a0, i32 0
  %ins1 = insertelement <4 x float> %ins0, float %a1, i32 1
  %ins2 = insertelement <4 x float> %ins1, float %a0, i32 2
  %ins3 = insertelement <4 x float> %ins2, float %a1, i32 3
  store <4 x float> %ins3, ptr %dst
  ret void
}

define void @buildvector_v2f64(ptr %dst, double %a0, double %a1) nounwind {
; CHECK-LABEL: buildvector_v2f64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    # kill: def $f1_64 killed $f1_64 def $vr1
; CHECK-NEXT:    # kill: def $f0_64 killed $f0_64 def $vr0
; CHECK-NEXT:    vextrins.d $vr0, $vr1, 16
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0 = insertelement <2 x double> undef, double %a0, i32 0
  %ins1 = insertelement <2 x double> %ins0, double %a1, i32 1
  store <2 x double> %ins1, ptr %dst
  ret void
}

define void @buildvector_v2f64_partial(ptr %dst, double %a1) nounwind {
; CHECK-LABEL: buildvector_v2f64_partial:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    # kill: def $f0_64 killed $f0_64 def $vr0
; CHECK-NEXT:    vextrins.d $vr0, $vr0, 16
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0 = insertelement <2 x double> undef, double undef, i32 0
  %ins1 = insertelement <2 x double> %ins0, double   %a1, i32 1
  store <2 x double> %ins1, ptr %dst
  ret void
}

define void @buildvector_v2f64_with_constant(ptr %dst, double %a0) nounwind {
; CHECK-LABEL: buildvector_v2f64_with_constant:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    # kill: def $f0_64 killed $f0_64 def $vr0
; CHECK-NEXT:    vldi $vr1, -1024
; CHECK-NEXT:    vpackev.d $vr0, $vr1, $vr0
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %ins0 = insertelement <2 x double> undef, double %a0, i32 0
  %ins1 = insertelement <2 x double> %ins0, double 2.0, i32 1
  store <2 x double> %ins1, ptr %dst
  ret void
}

;; If `isShuffleMaskLegal` returns true, it will lead to an infinite loop.
define void @extract1_i32_zext_insert0_i64_undef(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: extract1_i32_zext_insert0_i64_undef:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vld $vr0, $a0, 0
; CHECK-NEXT:    vsrli.d $vr0, $vr0, 32
; CHECK-NEXT:    vst $vr0, $a1, 0
; CHECK-NEXT:    ret
  %v = load volatile <4 x i32>, ptr %src
  %e = extractelement <4 x i32> %v, i32 1
  %z = zext i32 %e to i64
  %r = insertelement <2 x i64> undef, i64 %z, i32 0
  store <2 x i64> %r, ptr %dst
  ret void
}