; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s

define void @vadda_b(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: vadda_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vld $vr1, $a2, 0
; CHECK-NEXT:    vadda.b $vr0, $vr0, $vr1
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %va = load <16 x i8>, ptr %a
  %vb = load <16 x i8>, ptr %b
  %conda = icmp slt <16 x i8> %va, zeroinitializer
  %nega = sub <16 x i8> zeroinitializer, %va
  %absa = select <16 x i1> %conda, <16 x i8> %nega, <16 x i8> %va
  %condb = icmp slt <16 x i8> %vb, zeroinitializer
  %negb = sub <16 x i8> zeroinitializer, %vb
  %absb = select <16 x i1> %condb, <16 x i8> %negb, <16 x i8> %vb
  %add = add <16 x i8> %absa, %absb
  store <16 x i8> %add, ptr %res
  ret void
}

define void @vadda_h(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: vadda_h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vld $vr1, $a2, 0
; CHECK-NEXT:    vadda.h $vr0, $vr0, $vr1
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %va = load <8 x i16>, ptr %a
  %vb = load <8 x i16>, ptr %b
  %conda = icmp slt <8 x i16> %va, zeroinitializer
  %nega = sub <8 x i16> zeroinitializer, %va
  %absa = select <8 x i1> %conda, <8 x i16> %nega, <8 x i16> %va
  %condb = icmp slt <8 x i16> %vb, zeroinitializer
  %negb = sub <8 x i16> zeroinitializer, %vb
  %absb = select <8 x i1> %condb, <8 x i16> %negb, <8 x i16> %vb
  %add = add <8 x i16> %absa, %absb
  store <8 x i16> %add, ptr %res
  ret void
}

define void @vadda_w(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: vadda_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vld $vr1, $a2, 0
; CHECK-NEXT:    vadda.w $vr0, $vr0, $vr1
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %va = load <4 x i32>, ptr %a
  %vb = load <4 x i32>, ptr %b
  %conda = icmp slt <4 x i32> %va, zeroinitializer
  %nega = sub <4 x i32> zeroinitializer, %va
  %absa = select <4 x i1> %conda, <4 x i32> %nega, <4 x i32> %va
  %condb = icmp slt <4 x i32> %vb, zeroinitializer
  %negb = sub <4 x i32> zeroinitializer, %vb
  %absb = select <4 x i1> %condb, <4 x i32> %negb, <4 x i32> %vb
  %add = add <4 x i32> %absa, %absb
  store <4 x i32> %add, ptr %res
  ret void
}

define void @vadda_d(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: vadda_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vld $vr1, $a2, 0
; CHECK-NEXT:    vadda.d $vr0, $vr0, $vr1
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %va = load <2 x i64>, ptr %a
  %vb = load <2 x i64>, ptr %b
  %conda = icmp slt <2 x i64> %va, zeroinitializer
  %nega = sub <2 x i64> zeroinitializer, %va
  %absa = select <2 x i1> %conda, <2 x i64> %nega, <2 x i64> %va
  %condb = icmp slt <2 x i64> %vb, zeroinitializer
  %negb = sub <2 x i64> zeroinitializer, %vb
  %absb = select <2 x i1> %condb, <2 x i64> %negb, <2 x i64> %vb
  %add = add <2 x i64> %absa, %absb
  store <2 x i64> %add, ptr %res
  ret void
}