; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s

;; vilvl.b
define <16 x i8> @shufflevector_vilvl_v16i8(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: shufflevector_vilvl_v16i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vilvl.b $vr0, $vr1, $vr0
; CHECK-NEXT:    ret
    %c = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
    ret <16 x i8> %c
}

;; vilvl.h
define <8 x i16> @shufflevector_vilvl_v8i16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: shufflevector_vilvl_v8i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vilvl.h $vr0, $vr1, $vr0
; CHECK-NEXT:    ret
    %c = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
    ret <8 x i16> %c
}

;; vilvl.w
define <4 x i32> @shufflevector_vilvl_v4i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: shufflevector_vilvl_v4i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vilvl.w $vr0, $vr1, $vr0
; CHECK-NEXT:    ret
    %c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
    ret <4 x i32> %c
}

;; vilvl.w
define <4 x float> @shufflevector_vilvl_v4f32(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: shufflevector_vilvl_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vilvl.w $vr0, $vr1, $vr0
; CHECK-NEXT:    ret
    %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
    ret <4 x float> %c
}

;; vilvh.b
define <16 x i8> @shufflevector_vilvh_v16i8(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: shufflevector_vilvh_v16i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vilvh.b $vr0, $vr1, $vr0
; CHECK-NEXT:    ret
    %c = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
    ret <16 x i8> %c
}

;; vilvh.h
define <8 x i16> @shufflevector_vilvh_v8i16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: shufflevector_vilvh_v8i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vilvh.h $vr0, $vr1, $vr0
; CHECK-NEXT:    ret
    %c = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
    ret <8 x i16> %c
}

;; vilvh.w
define <4 x i32> @shufflevector_vilvh_v4i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: shufflevector_vilvh_v4i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vilvh.w $vr0, $vr1, $vr0
; CHECK-NEXT:    ret
    %c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
    ret <4 x i32> %c
}

;; vilvh.w
define <4 x float> @shufflevector_vilvh_v4f32(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: shufflevector_vilvh_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vilvh.w $vr0, $vr1, $vr0
; CHECK-NEXT:    ret
    %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
    ret <4 x float> %c
}