; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s

;; vpermi.w
define void @shufflevector_vpermi_v4i32(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: shufflevector_vpermi_v4i32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vld $vr1, $a2, 0
; CHECK-NEXT:    vpermi.w $vr1, $vr0, 78
; CHECK-NEXT:    vst $vr1, $a0, 0
; CHECK-NEXT:    ret
entry:
  %va = load <4 x i32>, ptr %a
  %vb = load <4 x i32>, ptr %b
  %c = shufflevector <4 x i32> %va, <4 x i32> %vb, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
  store <4 x i32> %c, ptr %res
  ret void
}

;; vpermi.w
define void @shufflevector_vpermi_v4f32(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: shufflevector_vpermi_v4f32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vld $vr1, $a2, 0
; CHECK-NEXT:    vpermi.w $vr0, $vr1, 141
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %va = load <4 x float>, ptr %a
  %vb = load <4 x float>, ptr %b
  %c = shufflevector <4 x float> %va, <4 x float> %vb, <4 x i32> <i32 5, i32 7, i32 0, i32 2>
  store <4 x float> %c, ptr %res
  ret void
}