; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64

define <32 x i8> @test_i8(<32 x i8> %shuffle) {
; CHECK-LABEL: test_i8:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vrepli.b $vr2, -85
; CHECK-NEXT:    vmuh.bu $vr0, $vr0, $vr2
; CHECK-NEXT:    vsrli.b $vr0, $vr0, 1
; CHECK-NEXT:    vmuh.bu $vr1, $vr1, $vr2
; CHECK-NEXT:    vsrli.b $vr1, $vr1, 1
; CHECK-NEXT:    ret
entry:
  %div = udiv <32 x i8> %shuffle, splat (i8 3)
  ret <32 x i8> %div
}

define <16 x i16> @test_i16(<16 x i16> %shuffle) {
; CHECK-LABEL: test_i16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lu12i.w $a0, 10
; CHECK-NEXT:    ori $a0, $a0, 2731
; CHECK-NEXT:    vreplgr2vr.h $vr2, $a0
; CHECK-NEXT:    vmuh.hu $vr0, $vr0, $vr2
; CHECK-NEXT:    vsrli.h $vr0, $vr0, 1
; CHECK-NEXT:    vmuh.hu $vr1, $vr1, $vr2
; CHECK-NEXT:    vsrli.h $vr1, $vr1, 1
; CHECK-NEXT:    ret
entry:
  %div = udiv <16 x i16> %shuffle, splat (i16 3)
  ret <16 x i16> %div
}

define <8 x i32> @test_i32(<8 x i32> %shuffle) {
; CHECK-LABEL: test_i32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lu12i.w $a0, -349526
; CHECK-NEXT:    ori $a0, $a0, 2731
; CHECK-NEXT:    vreplgr2vr.w $vr2, $a0
; CHECK-NEXT:    vmuh.wu $vr0, $vr0, $vr2
; CHECK-NEXT:    vsrli.w $vr0, $vr0, 1
; CHECK-NEXT:    vmuh.wu $vr1, $vr1, $vr2
; CHECK-NEXT:    vsrli.w $vr1, $vr1, 1
; CHECK-NEXT:    ret
entry:
  %div = udiv <8 x i32> %shuffle, splat (i32 3)
  ret <8 x i32> %div
}

define <4 x i64> @test_i64(<4 x i64> %shuffle) {
; LA32-LABEL: test_i64:
; LA32:       # %bb.0: # %entry
; LA32-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI3_0)
; LA32-NEXT:    vld $vr2, $a0, %pc_lo12(.LCPI3_0)
; LA32-NEXT:    vmuh.du $vr0, $vr0, $vr2
; LA32-NEXT:    vsrli.d $vr0, $vr0, 1
; LA32-NEXT:    vmuh.du $vr1, $vr1, $vr2
; LA32-NEXT:    vsrli.d $vr1, $vr1, 1
; LA32-NEXT:    ret
;
; LA64-LABEL: test_i64:
; LA64:       # %bb.0: # %entry
; LA64-NEXT:    lu12i.w $a0, -349526
; LA64-NEXT:    ori $a0, $a0, 2731
; LA64-NEXT:    lu32i.d $a0, -349526
; LA64-NEXT:    lu52i.d $a0, $a0, -1366
; LA64-NEXT:    vreplgr2vr.d $vr2, $a0
; LA64-NEXT:    vmuh.du $vr0, $vr0, $vr2
; LA64-NEXT:    vsrli.d $vr0, $vr0, 1
; LA64-NEXT:    vmuh.du $vr1, $vr1, $vr2
; LA64-NEXT:    vsrli.d $vr1, $vr1, 1
; LA64-NEXT:    ret
entry:
  %div = udiv <4 x i64> %shuffle, splat (i64 3)
  ret <4 x i64> %div
}