; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s

define <4 x i32> @test(<4 x i32> %conv22) {
; CHECK-LABEL: test:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vldi $vr1, -2305
; CHECK-NEXT:    lu12i.w $a0, -524280
; CHECK-NEXT:    ori $a0, $a0, 1
; CHECK-NEXT:    vreplgr2vr.w $vr2, $a0
; CHECK-NEXT:    vmuh.wu $vr2, $vr0, $vr2
; CHECK-NEXT:    vsrli.w $vr2, $vr2, 15
; CHECK-NEXT:    vmsub.w $vr0, $vr2, $vr1
; CHECK-NEXT:    ret
entry:
  %bc.i = bitcast <16 x i8> zeroinitializer to <8 x i16>
  %vecext.i = extractelement <8 x i16> %bc.i, i64 0
  %not.i1 = xor i16 %vecext.i, -1
  %vecinit24 = insertelement <4 x i16> zeroinitializer, i16 %not.i1, i64 0
  %vecinit27 = shufflevector <4 x i16> %vecinit24, <4 x i16> zeroinitializer, <4 x i32> zeroinitializer
  %conv28 = zext <4 x i16> %vecinit27 to <4 x i32>
  %rem = urem <4 x i32> %conv22, %conv28
  ret <4 x i32> %rem
}