; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s

define i8 @test(<2 x i32> %vecinit7) {
; CHECK-LABEL: test:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vrepli.d $vr1, 1
; CHECK-NEXT:    vand.v $vr0, $vr0, $vr1
; CHECK-NEXT:    vneg.d $vr0, $vr0
; CHECK-NEXT:    vpickve2gr.b $a0, $vr0, 4
; CHECK-NEXT:    ret
entry:
  %0 = tail call <16 x i8> @llvm.loongarch.lsx.vadd.b(<16 x i8> splat (i8 1), <16 x i8> zeroinitializer)
  %shuffle = shufflevector <16 x i8> %0, <16 x i8> zeroinitializer, <2 x i32> <i32 2, i32 0>
  %1 = and <2 x i8> %shuffle, splat (i8 1)
  %and = zext <2 x i8> %1 to <2 x i32>
  %and.i = and <2 x i32> %vecinit7, %and
  %conv.i = zext <2 x i32> %and.i to <2 x i64>
  %sub.i = sub <2 x i64> zeroinitializer, %conv.i
  %2 = bitcast <2 x i64> %sub.i to <16 x i8>
  %conv14 = extractelement <16 x i8> %2, i64 4
  ret i8 %conv14
}

declare <16 x i8> @llvm.loongarch.lsx.vadd.b(<16 x i8>, <16 x i8>)