; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s

define <16 x i8> @srlr_b(<16 x i8> %a, <16 x i8> %b) nounwind {
; CHECK-LABEL: srlr_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsrlr.b $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %0 = lshr <16 x i8> %a, %b
  %1 = add <16 x i8> %b, splat (i8 -1)
  %2 = lshr <16 x i8> %a, %1
  %3 = and <16 x i8> %2, splat (i8 1)
  %4 = add <16 x i8> %3, %0
  %5 = icmp eq <16 x i8> %b, zeroinitializer
  %6 = select <16 x i1> %5, <16 x i8> %a, <16 x i8> %4
  ret <16 x i8> %6
}

define <8 x i16> @srlr_h(<8 x i16> %a, <8 x i16> %b) nounwind {
; CHECK-LABEL: srlr_h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsrlr.h $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %0 = lshr <8 x i16> %a, %b
  %1 = add <8 x i16> %b, splat (i16 -1)
  %2 = lshr <8 x i16> %a, %1
  %3 = and <8 x i16> %2, splat (i16 1)
  %4 = add <8 x i16> %3, %0
  %5 = icmp eq <8 x i16> %b, zeroinitializer
  %6 = select <8 x i1> %5, <8 x i16> %a, <8 x i16> %4
  ret <8 x i16> %6
}

define <4 x i32> @srlr_w(<4 x i32> %a, <4 x i32> %b) nounwind {
; CHECK-LABEL: srlr_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsrlr.w $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %0 = lshr <4 x i32> %a, %b
  %1 = add <4 x i32> %b, splat (i32 -1)
  %2 = lshr <4 x i32> %a, %1
  %3 = and <4 x i32> %2, splat (i32 1)
  %4 = add <4 x i32> %3, %0
  %5 = icmp eq <4 x i32> %b, zeroinitializer
  %6 = select <4 x i1> %5, <4 x i32> %a, <4 x i32> %4
  ret <4 x i32> %6
}

define <2 x i64> @srlr_d(<2 x i64> %a, <2 x i64> %b) nounwind {
; CHECK-LABEL: srlr_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsrlr.d $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %0 = lshr <2 x i64> %a, %b
  %1 = add <2 x i64> %b, splat (i64 -1)
  %2 = lshr <2 x i64> %a, %1
  %3 = and <2 x i64> %2, splat (i64 1)
  %4 = add <2 x i64> %3, %0
  %5 = icmp eq <2 x i64> %b, zeroinitializer
  %6 = select <2 x i1> %5, <2 x i64> %a, <2 x i64> %4
  ret <2 x i64> %6
}

define <16 x i8> @srlr_b_1(<16 x i8> %a) nounwind {
; CHECK-LABEL: srlr_b_1:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsrlri.b $vr0, $vr0, 1
; CHECK-NEXT:    ret
entry:
  %0 = lshr <16 x i8> %a, splat (i8 1)
  %1 = and <16 x i8> %a, splat (i8 1)
  %2 = add nsw <16 x i8> %1, %0
  ret <16 x i8> %2
}

define <16 x i8> @srlr_b_7(<16 x i8> %a) nounwind {
; CHECK-LABEL: srlr_b_7:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsrlri.b $vr0, $vr0, 7
; CHECK-NEXT:    ret
entry:
  %0 = lshr <16 x i8> %a, splat (i8 7)
  %1 = lshr <16 x i8> %a, splat (i8 6)
  %2 = and <16 x i8> %1, splat (i8 1)
  %3 = add nsw <16 x i8> %2, %0
  ret <16 x i8> %3
}

define <8 x i16> @srlr_h_1(<8 x i16> %a) nounwind {
; CHECK-LABEL: srlr_h_1:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsrlri.h $vr0, $vr0, 1
; CHECK-NEXT:    ret
entry:
  %0 = lshr <8 x i16> %a, splat (i16 1)
  %1 = and <8 x i16> %a, splat (i16 1)
  %2 = add nsw <8 x i16> %1, %0
  ret <8 x i16> %2
}

define <8 x i16> @srlr_h_15(<8 x i16> %a) nounwind {
; CHECK-LABEL: srlr_h_15:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsrlri.h $vr0, $vr0, 15
; CHECK-NEXT:    ret
entry:
  %0 = lshr <8 x i16> %a, splat (i16 15)
  %1 = lshr <8 x i16> %a, splat (i16 14)
  %2 = and <8 x i16> %1, splat (i16 1)
  %3 = add nsw <8 x i16> %2, %0
  ret <8 x i16> %3
}

define <4 x i32> @srlr_w_1(<4 x i32> %a) nounwind {
; CHECK-LABEL: srlr_w_1:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsrlri.w $vr0, $vr0, 1
; CHECK-NEXT:    ret
entry:
  %0 = lshr <4 x i32> %a, splat (i32 1)
  %1 = and <4 x i32> %a, splat (i32 1)
  %2 = add nsw <4 x i32> %1, %0
  ret <4 x i32> %2
}

define <4 x i32> @srlr_w_31(<4 x i32> %a) nounwind {
; CHECK-LABEL: srlr_w_31:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsrlri.w $vr0, $vr0, 31
; CHECK-NEXT:    ret
entry:
  %0 = lshr <4 x i32> %a, splat (i32 31)
  %1 = lshr <4 x i32> %a, splat (i32 30)
  %2 = and <4 x i32> %1, splat (i32 1)
  %3 = add nsw <4 x i32> %2, %0
  ret <4 x i32> %3
}

define <2 x i64> @srlr_d_1(<2 x i64> %a) nounwind {
; CHECK-LABEL: srlr_d_1:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsrlri.d $vr0, $vr0, 1
; CHECK-NEXT:    ret
entry:
  %0 = lshr <2 x i64> %a, splat (i64 1)
  %1 = and <2 x i64> %a, splat (i64 1)
  %2 = add nsw <2 x i64> %1, %0
  ret <2 x i64> %2
}

define <2 x i64> @srlr_d_63(<2 x i64> %a) nounwind {
; CHECK-LABEL: srlr_d_63:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsrlri.d $vr0, $vr0, 63
; CHECK-NEXT:    ret
entry:
  %0 = lshr <2 x i64> %a, splat (i64 63)
  %1 = lshr <2 x i64> %a, splat (i64 62)
  %2 = and <2 x i64> %1, splat (i64 1)
  %3 = add nsw <2 x i64> %2, %0
  ret <2 x i64> %3
}