; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_80 -mattr=+ptx81 | FileCheck %s
; RUN: %if ptxas-sm_80 && ptxas-isa-8.1 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_80 -mattr=+ptx81 | %ptxas-verify -arch=sm_80 %}

; CHECK-LABEL: cvt_rna_satfinite_tf32_f32
define i32 @cvt_rna_satfinite_tf32_f32(float %f1) {
; CHECK-LABEL: cvt_rna_satfinite_tf32_f32(
; CHECK:       {
; CHECK-NEXT:    .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.b32 %r1, [cvt_rna_satfinite_tf32_f32_param_0];
; CHECK-NEXT:    cvt.rna.satfinite.tf32.f32 %r2, %r1;
; CHECK-NEXT:    st.param.b32 [func_retval0], %r2;
; CHECK-NEXT:    ret;
  %val = call i32 @llvm.nvvm.f2tf32.rna.satfinite(float %f1)
  ret i32 %val
}

define <2 x bfloat> @cvt_rn_bf16x2_f32_sf(float %f1, float %f2) {
; CHECK-LABEL: cvt_rn_bf16x2_f32_sf(
; CHECK:       {
; CHECK-NEXT:    .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.b32 %r1, [cvt_rn_bf16x2_f32_sf_param_0];
; CHECK-NEXT:    ld.param.b32 %r2, [cvt_rn_bf16x2_f32_sf_param_1];
; CHECK-NEXT:    cvt.rn.satfinite.bf16x2.f32 %r3, %r1, %r2;
; CHECK-NEXT:    st.param.b32 [func_retval0], %r3;
; CHECK-NEXT:    ret;
  %val = call <2 x bfloat> @llvm.nvvm.ff2bf16x2.rn.satfinite(float %f1, float %f2)
  ret <2 x bfloat> %val
}

define <2 x bfloat> @cvt_rn_relu_bf16x2_f32_sf(float %f1, float %f2) {
; CHECK-LABEL: cvt_rn_relu_bf16x2_f32_sf(
; CHECK:       {
; CHECK-NEXT:    .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.b32 %r1, [cvt_rn_relu_bf16x2_f32_sf_param_0];
; CHECK-NEXT:    ld.param.b32 %r2, [cvt_rn_relu_bf16x2_f32_sf_param_1];
; CHECK-NEXT:    cvt.rn.relu.satfinite.bf16x2.f32 %r3, %r1, %r2;
; CHECK-NEXT:    st.param.b32 [func_retval0], %r3;
; CHECK-NEXT:    ret;
  %val = call <2 x bfloat> @llvm.nvvm.ff2bf16x2.rn.relu.satfinite(float %f1, float %f2)
  ret <2 x bfloat> %val
}

define <2 x bfloat> @cvt_rz_bf16x2_f32_sf(float %f1, float %f2) {
; CHECK-LABEL: cvt_rz_bf16x2_f32_sf(
; CHECK:       {
; CHECK-NEXT:    .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.b32 %r1, [cvt_rz_bf16x2_f32_sf_param_0];
; CHECK-NEXT:    ld.param.b32 %r2, [cvt_rz_bf16x2_f32_sf_param_1];
; CHECK-NEXT:    cvt.rz.satfinite.bf16x2.f32 %r3, %r1, %r2;
; CHECK-NEXT:    st.param.b32 [func_retval0], %r3;
; CHECK-NEXT:    ret;
  %val = call <2 x bfloat> @llvm.nvvm.ff2bf16x2.rz.satfinite(float %f1, float %f2)
  ret <2 x bfloat> %val
}

define <2 x bfloat> @cvt_rz_relu_bf16x2_f32_sf(float %f1, float %f2) {
; CHECK-LABEL: cvt_rz_relu_bf16x2_f32_sf(
; CHECK:       {
; CHECK-NEXT:    .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.b32 %r1, [cvt_rz_relu_bf16x2_f32_sf_param_0];
; CHECK-NEXT:    ld.param.b32 %r2, [cvt_rz_relu_bf16x2_f32_sf_param_1];
; CHECK-NEXT:    cvt.rz.relu.satfinite.bf16x2.f32 %r3, %r1, %r2;
; CHECK-NEXT:    st.param.b32 [func_retval0], %r3;
; CHECK-NEXT:    ret;
  %val = call <2 x bfloat> @llvm.nvvm.ff2bf16x2.rz.relu.satfinite(float %f1, float %f2)
  ret <2 x bfloat> %val
}

declare <2 x bfloat> @llvm.nvvm.ff2bf16x2.rn.satfinite(float, float)
declare <2 x bfloat> @llvm.nvvm.ff2bf16x2.rn.relu.satfinite(float, float)
declare <2 x bfloat> @llvm.nvvm.ff2bf16x2.rz.satfinite(float, float)
declare <2 x bfloat> @llvm.nvvm.ff2bf16x2.rz.relu.satfinite(float, float)

define <2 x half> @cvt_rn_f16x2_f32_sf(float %f1, float %f2) {
; CHECK-LABEL: cvt_rn_f16x2_f32_sf(
; CHECK:       {
; CHECK-NEXT:    .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.b32 %r1, [cvt_rn_f16x2_f32_sf_param_0];
; CHECK-NEXT:    ld.param.b32 %r2, [cvt_rn_f16x2_f32_sf_param_1];
; CHECK-NEXT:    cvt.rn.satfinite.f16x2.f32 %r3, %r1, %r2;
; CHECK-NEXT:    st.param.b32 [func_retval0], %r3;
; CHECK-NEXT:    ret;
  %val = call <2 x half> @llvm.nvvm.ff2f16x2.rn.satfinite(float %f1, float %f2)
  ret <2 x half> %val
}

define <2 x half> @cvt_rn_relu_f16x2_f32_sf(float %f1, float %f2) {
; CHECK-LABEL: cvt_rn_relu_f16x2_f32_sf(
; CHECK:       {
; CHECK-NEXT:    .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.b32 %r1, [cvt_rn_relu_f16x2_f32_sf_param_0];
; CHECK-NEXT:    ld.param.b32 %r2, [cvt_rn_relu_f16x2_f32_sf_param_1];
; CHECK-NEXT:    cvt.rn.relu.satfinite.f16x2.f32 %r3, %r1, %r2;
; CHECK-NEXT:    st.param.b32 [func_retval0], %r3;
; CHECK-NEXT:    ret;
  %val = call <2 x half> @llvm.nvvm.ff2f16x2.rn.relu.satfinite(float %f1, float %f2)
  ret <2 x half> %val
}

define <2 x half> @cvt_rz_f16x2_f32_sf(float %f1, float %f2) {
; CHECK-LABEL: cvt_rz_f16x2_f32_sf(
; CHECK:       {
; CHECK-NEXT:    .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.b32 %r1, [cvt_rz_f16x2_f32_sf_param_0];
; CHECK-NEXT:    ld.param.b32 %r2, [cvt_rz_f16x2_f32_sf_param_1];
; CHECK-NEXT:    cvt.rz.satfinite.f16x2.f32 %r3, %r1, %r2;
; CHECK-NEXT:    st.param.b32 [func_retval0], %r3;
; CHECK-NEXT:    ret;
  %val = call <2 x half> @llvm.nvvm.ff2f16x2.rz.satfinite(float %f1, float %f2)
  ret <2 x half> %val
}

define <2 x half> @cvt_rz_relu_f16x2_f32_sf(float %f1, float %f2) {
; CHECK-LABEL: cvt_rz_relu_f16x2_f32_sf(
; CHECK:       {
; CHECK-NEXT:    .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.b32 %r1, [cvt_rz_relu_f16x2_f32_sf_param_0];
; CHECK-NEXT:    ld.param.b32 %r2, [cvt_rz_relu_f16x2_f32_sf_param_1];
; CHECK-NEXT:    cvt.rz.relu.satfinite.f16x2.f32 %r3, %r1, %r2;
; CHECK-NEXT:    st.param.b32 [func_retval0], %r3;
; CHECK-NEXT:    ret;
  %val = call <2 x half> @llvm.nvvm.ff2f16x2.rz.relu.satfinite(float %f1, float %f2)
  ret <2 x half> %val
}

declare <2 x half> @llvm.nvvm.ff2f16x2.rn.satfinite(float, float)
declare <2 x half> @llvm.nvvm.ff2f16x2.rn.relu.satfinite(float, float)
declare <2 x half> @llvm.nvvm.ff2f16x2.rz.satfinite(float, float)
declare <2 x half> @llvm.nvvm.ff2f16x2.rz.relu.satfinite(float, float)

define bfloat @cvt_rn_bf16_f32_sf(float %f1) {
; CHECK-LABEL: cvt_rn_bf16_f32_sf(
; CHECK:       {
; CHECK-NEXT:    .reg .b16 %rs<2>;
; CHECK-NEXT:    .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.b32 %r1, [cvt_rn_bf16_f32_sf_param_0];
; CHECK-NEXT:    cvt.rn.satfinite.bf16.f32 %rs1, %r1;
; CHECK-NEXT:    st.param.b16 [func_retval0], %rs1;
; CHECK-NEXT:    ret;
  %val = call bfloat @llvm.nvvm.f2bf16.rn.satfinite(float %f1)
  ret bfloat %val
}

define bfloat @cvt_rn_relu_bf16_f32_sf(float %f1) {
; CHECK-LABEL: cvt_rn_relu_bf16_f32_sf(
; CHECK:       {
; CHECK-NEXT:    .reg .b16 %rs<2>;
; CHECK-NEXT:    .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.b32 %r1, [cvt_rn_relu_bf16_f32_sf_param_0];
; CHECK-NEXT:    cvt.rn.relu.satfinite.bf16.f32 %rs1, %r1;
; CHECK-NEXT:    st.param.b16 [func_retval0], %rs1;
; CHECK-NEXT:    ret;
  %val = call bfloat @llvm.nvvm.f2bf16.rn.relu.satfinite(float %f1)
  ret bfloat %val
}

define bfloat @cvt_rz_bf16_f32_sf(float %f1) {
; CHECK-LABEL: cvt_rz_bf16_f32_sf(
; CHECK:       {
; CHECK-NEXT:    .reg .b16 %rs<2>;
; CHECK-NEXT:    .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.b32 %r1, [cvt_rz_bf16_f32_sf_param_0];
; CHECK-NEXT:    cvt.rz.satfinite.bf16.f32 %rs1, %r1;
; CHECK-NEXT:    st.param.b16 [func_retval0], %rs1;
; CHECK-NEXT:    ret;
  %val = call bfloat @llvm.nvvm.f2bf16.rz.satfinite(float %f1)
  ret bfloat %val
}

define bfloat @cvt_rz_relu_bf16_f32_sf(float %f1) {
; CHECK-LABEL: cvt_rz_relu_bf16_f32_sf(
; CHECK:       {
; CHECK-NEXT:    .reg .b16 %rs<2>;
; CHECK-NEXT:    .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.b32 %r1, [cvt_rz_relu_bf16_f32_sf_param_0];
; CHECK-NEXT:    cvt.rz.relu.satfinite.bf16.f32 %rs1, %r1;
; CHECK-NEXT:    st.param.b16 [func_retval0], %rs1;
; CHECK-NEXT:    ret;
  %val = call bfloat @llvm.nvvm.f2bf16.rz.relu.satfinite(float %f1)
  ret bfloat %val
}

declare bfloat @llvm.nvvm.f2bf16.rn.satfinite(float)
declare bfloat @llvm.nvvm.f2bf16.rn.relu.satfinite(float)
declare bfloat @llvm.nvvm.f2bf16.rz.satfinite(float)
declare bfloat @llvm.nvvm.f2bf16.rz.relu.satfinite(float)

define half @cvt_rn_f16_f32_sf(float %f1) {
; CHECK-LABEL: cvt_rn_f16_f32_sf(
; CHECK:       {
; CHECK-NEXT:    .reg .b16 %rs<2>;
; CHECK-NEXT:    .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.b32 %r1, [cvt_rn_f16_f32_sf_param_0];
; CHECK-NEXT:    cvt.rn.satfinite.f16.f32 %rs1, %r1;
; CHECK-NEXT:    st.param.b16 [func_retval0], %rs1;
; CHECK-NEXT:    ret;
  %val = call half @llvm.nvvm.f2f16.rn.satfinite(float %f1)
  ret half %val
}

define half @cvt_rn_relu_f16_f32_sf(float %f1) {
; CHECK-LABEL: cvt_rn_relu_f16_f32_sf(
; CHECK:       {
; CHECK-NEXT:    .reg .b16 %rs<2>;
; CHECK-NEXT:    .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.b32 %r1, [cvt_rn_relu_f16_f32_sf_param_0];
; CHECK-NEXT:    cvt.rn.relu.satfinite.f16.f32 %rs1, %r1;
; CHECK-NEXT:    st.param.b16 [func_retval0], %rs1;
; CHECK-NEXT:    ret;
  %val = call half @llvm.nvvm.f2f16.rn.relu.satfinite(float %f1)
  ret half %val
}

define half @cvt_rz_f16_f32_sf(float %f1) {
; CHECK-LABEL: cvt_rz_f16_f32_sf(
; CHECK:       {
; CHECK-NEXT:    .reg .b16 %rs<2>;
; CHECK-NEXT:    .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.b32 %r1, [cvt_rz_f16_f32_sf_param_0];
; CHECK-NEXT:    cvt.rz.satfinite.f16.f32 %rs1, %r1;
; CHECK-NEXT:    st.param.b16 [func_retval0], %rs1;
; CHECK-NEXT:    ret;
  %val = call half @llvm.nvvm.f2f16.rz.satfinite(float %f1)
  ret half %val
}

define half @cvt_rz_relu_f16_f32_sf(float %f1) {
; CHECK-LABEL: cvt_rz_relu_f16_f32_sf(
; CHECK:       {
; CHECK-NEXT:    .reg .b16 %rs<2>;
; CHECK-NEXT:    .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.b32 %r1, [cvt_rz_relu_f16_f32_sf_param_0];
; CHECK-NEXT:    cvt.rz.relu.satfinite.f16.f32 %rs1, %r1;
; CHECK-NEXT:    st.param.b16 [func_retval0], %rs1;
; CHECK-NEXT:    ret;
  %val = call half @llvm.nvvm.f2f16.rz.relu.satfinite(float %f1)
  ret half %val
}

declare half @llvm.nvvm.f2f16.rn.satfinite(float)
declare half @llvm.nvvm.f2f16.rn.relu.satfinite(float)
declare half @llvm.nvvm.f2f16.rz.satfinite(float)
declare half @llvm.nvvm.f2f16.rz.relu.satfinite(float)