# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=nvptx64 -mcpu=sm_20 -run-pass=early-machinelicm %s -o - | FileCheck %s

# This test checks that the early-machineLICM pass successfully creates a new
# loop preheader by splitting the critical edge and hoisting the loop invariant
# value `%8` to the preheader.
# Since the critical edge successor is a loop header, the splitting does not
# break the structured CFG, which is a requirement for the NVPTX target.

---
name:            test_hoist
tracksRegLiveness: true
registers:
  - { id: 0, class: b64, preferred-register: '', flags: [  ] }
  - { id: 1, class: b32, preferred-register: '', flags: [  ] }
  - { id: 2, class: b32, preferred-register: '', flags: [  ] }
  - { id: 3, class: b32, preferred-register: '', flags: [  ] }
  - { id: 4, class: b32, preferred-register: '', flags: [  ] }
  - { id: 5, class: b32, preferred-register: '', flags: [  ] }
  - { id: 6, class: b64, preferred-register: '', flags: [  ] }
  - { id: 7, class: b1, preferred-register: '', flags: [  ] }
  - { id: 8, class: b32, preferred-register: '', flags: [  ] }
  - { id: 9, class: b1, preferred-register: '', flags: [  ] }
body:             |
  ; CHECK-LABEL: name: test_hoist
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   successors: %bb.2(0x30000000), %bb.3(0x50000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[LD_i32_:%[0-9]+]]:b32 = LD_i32 0, 0, 101, 3, 32, -1, &test_hoist_param_1, 0 :: (dereferenceable invariant load (s32), addrspace 101)
  ; CHECK-NEXT:   [[LD_i64_:%[0-9]+]]:b64 = LD_i64 0, 0, 101, 3, 64, -1, &test_hoist_param_0, 0 :: (dereferenceable invariant load (s64), addrspace 101)
  ; CHECK-NEXT:   [[ADD64ri:%[0-9]+]]:b64 = nuw ADD64ri killed [[LD_i64_]], 2
  ; CHECK-NEXT:   [[LD_i32_1:%[0-9]+]]:b32 = LD_i32 0, 0, 1, 3, 32, -1, [[ADD64ri]], 0
  ; CHECK-NEXT:   [[SETP_i32ri:%[0-9]+]]:b1 = SETP_i32ri [[LD_i32_]], 0, 0
  ; CHECK-NEXT:   CBranch killed [[SETP_i32ri]], %bb.2, 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[ADD32ri:%[0-9]+]]:b32 = ADD32ri [[LD_i32_]], -1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x04000000), %bb.1(0x7c000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:b32 = PHI [[LD_i32_1]], %bb.3, %3, %bb.1
  ; CHECK-NEXT:   [[SREM32rr:%[0-9]+]]:b32 = SREM32rr [[PHI]], [[ADD32ri]]
  ; CHECK-NEXT:   [[SETP_i32ri1:%[0-9]+]]:b1 = SETP_i32ri [[SREM32rr]], 0, 1
  ; CHECK-NEXT:   CBranch killed [[SETP_i32ri1]], %bb.1, 0
  ; CHECK-NEXT:   GOTO %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   [[PHI1:%[0-9]+]]:b32 = PHI [[LD_i32_1]], %bb.0, [[SREM32rr]], %bb.1
  ; CHECK-NEXT:   ST_i32 [[PHI1]], 0, 0, 1, 32, [[ADD64ri]], 0
  ; CHECK-NEXT:   Return
  bb.0.entry:
    successors: %bb.2(0x30000000), %bb.1(0x50000000)

    %5:b32 = LD_i32 0, 0, 101, 3, 32, -1, &test_hoist_param_1, 0 :: (dereferenceable invariant load (s32), addrspace 101)
    %6:b64 = LD_i64 0, 0, 101, 3, 64, -1, &test_hoist_param_0, 0 :: (dereferenceable invariant load (s64), addrspace 101)
    %0:b64 = nuw ADD64ri killed %6, 2
    %1:b32 = LD_i32 0, 0, 1, 3, 32, -1, %0, 0
    %7:b1 = SETP_i32ri %5, 0, 0
    CBranch killed %7, %bb.2, 0
    GOTO %bb.1


  bb.1:
    successors: %bb.2(0x04000000), %bb.1(0x7c000000)

    %2:b32 = PHI %1, %bb.0, %3, %bb.1
    %8:b32 = ADD32ri %5, -1
    %3:b32 = SREM32rr %2, %8
    %9:b1 = SETP_i32ri %3, 0, 1
    CBranch killed %9, %bb.1, 0
    GOTO %bb.2

  bb.2:
    %4:b32 = PHI %1, %bb.0, %3, %bb.1
    ST_i32 %4, 0, 0, 1, 32, %0, 0
    Return
...