; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -S -nvptx-mark-kernel-ptrs-global | FileCheck %s --check-prefix IR
; RUN: llc < %s -mcpu=sm_20 --mtriple nvptx64-nvidia-cuda | FileCheck %s --check-prefixes PTXC
; RUN: llc < %s -mcpu=sm_20 --mtriple nvptx64-nvidia-nvcl | FileCheck %s --check-prefixes PTXO
; RUN: %if ptxas %{ llc < %s -mcpu=sm_20 | %ptxas-verify %}

target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64"
target triple = "nvptx64-nvidia-cuda"

define ptx_kernel void @ptr_as_int(i64 noundef %i, i32 noundef %v) {
; IR-LABEL: define ptx_kernel void @ptr_as_int(
; IR-SAME: i64 noundef [[I:%.*]], i32 noundef [[V:%.*]]) {
; IR-NEXT:    [[P:%.*]] = inttoptr i64 [[I]] to ptr
; IR-NEXT:    [[P1:%.*]] = addrspacecast ptr [[P]] to ptr addrspace(1)
; IR-NEXT:    [[P2:%.*]] = addrspacecast ptr addrspace(1) [[P1]] to ptr
; IR-NEXT:    store i32 [[V]], ptr [[P2]], align 4
; IR-NEXT:    ret void
;
; PTXC-LABEL: ptr_as_int(
; PTXC:       {
; PTXC-NEXT:    .reg .b32 %r<2>;
; PTXC-NEXT:    .reg .b64 %rd<3>;
; PTXC-EMPTY:
; PTXC-NEXT:  // %bb.0:
; PTXC-NEXT:    ld.param.b64 %rd1, [ptr_as_int_param_0];
; PTXC-NEXT:    ld.param.b32 %r1, [ptr_as_int_param_1];
; PTXC-NEXT:    cvta.to.global.u64 %rd2, %rd1;
; PTXC-NEXT:    st.global.b32 [%rd2], %r1;
; PTXC-NEXT:    ret;
; PTXO-LABEL: ptr_as_int(
; PTXO:       {
; PTXO-NEXT:    .reg .b32 %r<2>;
; PTXO-NEXT:    .reg .b64 %rd<2>;
; PTXO-EMPTY:
; PTXO-NEXT:  // %bb.0:
; PTXO-NEXT:    ld.param.b64 %rd1, [ptr_as_int_param_0];
; PTXO-NEXT:    ld.param.b32 %r1, [ptr_as_int_param_1];
; PTXO-NEXT:    st.b32 [%rd1], %r1;
; PTXO-NEXT:    ret;
  %p = inttoptr i64 %i to ptr
  store i32 %v, ptr %p, align 4
  ret void
}

%struct.S = type { i64 }

define ptx_kernel void @ptr_as_int_aggr(ptr nocapture noundef readonly byval(%struct.S) align 8 %s, i32 noundef %v) {
; IR-LABEL: define ptx_kernel void @ptr_as_int_aggr(
; IR-SAME: ptr noundef readonly byval([[STRUCT_S:%.*]]) align 8 captures(none) [[S:%.*]], i32 noundef [[V:%.*]]) {
; IR-NEXT:    [[I:%.*]] = load i64, ptr [[S]], align 8
; IR-NEXT:    [[P:%.*]] = inttoptr i64 [[I]] to ptr
; IR-NEXT:    [[P1:%.*]] = addrspacecast ptr [[P]] to ptr addrspace(1)
; IR-NEXT:    [[P2:%.*]] = addrspacecast ptr addrspace(1) [[P1]] to ptr
; IR-NEXT:    store i32 [[V]], ptr [[P2]], align 4
; IR-NEXT:    ret void
;
; PTXC-LABEL: ptr_as_int_aggr(
; PTXC:       {
; PTXC-NEXT:    .reg .b32 %r<2>;
; PTXC-NEXT:    .reg .b64 %rd<3>;
; PTXC-EMPTY:
; PTXC-NEXT:  // %bb.0:
; PTXC-NEXT:    ld.param.b32 %r1, [ptr_as_int_aggr_param_1];
; PTXC-NEXT:    ld.param.b64 %rd1, [ptr_as_int_aggr_param_0];
; PTXC-NEXT:    cvta.to.global.u64 %rd2, %rd1;
; PTXC-NEXT:    st.global.b32 [%rd2], %r1;
; PTXC-NEXT:    ret;
; PTXO-LABEL: ptr_as_int_aggr(
; PTXO:       {
; PTXO-NEXT:    .reg .b32 %r<2>;
; PTXO-NEXT:    .reg .b64 %rd<2>;
; PTXO-EMPTY:
; PTXO-NEXT:  // %bb.0:
; PTXO-NEXT:    ld.param.b32 %r1, [ptr_as_int_aggr_param_1];
; PTXO-NEXT:    ld.param.b64 %rd1, [ptr_as_int_aggr_param_0];
; PTXO-NEXT:    st.b32 [%rd1], %r1;
; PTXO-NEXT:    ret;
  %i = load i64, ptr %s, align 8
  %p = inttoptr i64 %i to ptr
  store i32 %v, ptr %p, align 4
  ret void
}