; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -verify-machineinstrs -mcpu=ppc -mtriple=powerpc64-ibm-aix < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=future \ ; RUN: -mtriple=powerpc64-ibm-aix < %s | FileCheck %s --check-prefix=CHECK-WACC target datalayout = "E-m:a-Fi64-i64:64-n32:64-S128-v256:256:256-v512:512:512" define void @baz(i64 %arg) local_unnamed_addr #0 { ; CHECK-LABEL: baz: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: xxmfacc 0 ; CHECK-NEXT: xxmrgld 0, 0, 2 ; CHECK-NEXT: xxlxor 1, 1, 1 ; CHECK-NEXT: xvnegdp 2, 0 ; CHECK-NEXT: xvnegdp 0, 0 ; CHECK-NEXT: xvsubdp 2, 2, 1 ; CHECK-NEXT: xvsubdp 0, 0, 3 ; CHECK-NEXT: xvmuldp 2, 2, 1 ; CHECK-NEXT: xvmuldp 0, 0, 1 ; CHECK-NEXT: xvmaddadp 2, 1, 1 ; CHECK-NEXT: xvmaddadp 0, 1, 1 ; CHECK-NEXT: xvadddp 2, 2, 1 ; CHECK-NEXT: xvadddp 0, 0, 1 ; CHECK-NEXT: stxv 2, 0(3) ; CHECK-NEXT: stxv 0, 0(3) ; CHECK-NEXT: # implicit-def: $acc0 ; CHECK-NEXT: bc 12, 20, L..BB0_2 ; CHECK-NEXT: # %bb.1: # %bb10 ; CHECK-NEXT: xvf64gerpp 0, 34, 0 ; CHECK-NEXT: L..BB0_2: # %bb12 ; CHECK-NEXT: cmpdi 3, 0 ; CHECK-NEXT: L..BB0_3: # %bb13 ; CHECK-NEXT: # ; CHECK-NEXT: bc 4, 2, L..BB0_3 ; CHECK-NEXT: # %bb.4: # %bb14 ; CHECK-NEXT: xxmfacc 0 ; CHECK-NEXT: xxlxor 0, 0, 0 ; CHECK-NEXT: xxlxor 2, 2, 2 ; CHECK-NEXT: xvsubdp 1, 0, 1 ; CHECK-NEXT: xvmaddadp 2, 1, 2 ; CHECK-NEXT: xvadddp 0, 2, 0 ; CHECK-NEXT: xxswapd 0, 0 ; CHECK-NEXT: stxv 0, 0(3) ; CHECK-NEXT: blr ; ; CHECK-WACC-LABEL: baz: ; CHECK-WACC: # %bb.0: # %bb ; CHECK-WACC-NEXT: dmxxextfdmr512 34, 36, 0, 0 ; CHECK-WACC-NEXT: xxmrgld 1, 34, 36 ; CHECK-WACC-NEXT: xxswapd 2, 1 ; CHECK-WACC-NEXT: xxlxor 0, 0, 0 ; CHECK-WACC-NEXT: xvnegdp 1, 1 ; CHECK-WACC-NEXT: xvnegdp 2, 2 ; CHECK-WACC-NEXT: xvsubdp 1, 1, 0 ; CHECK-WACC-NEXT: xvsubdp 2, 2, 37 ; CHECK-WACC-NEXT: xvmuldp 1, 1, 0 ; CHECK-WACC-NEXT: xvmuldp 2, 2, 0 ; CHECK-WACC-NEXT: xvmaddadp 1, 0, 0 ; CHECK-WACC-NEXT: xvmaddadp 2, 0, 0 ; CHECK-WACC-NEXT: xvadddp 1, 1, 0 ; CHECK-WACC-NEXT: xvadddp 0, 2, 0 ; CHECK-WACC-NEXT: stxv 1, 0(3) ; CHECK-WACC-NEXT: stxv 0, 0(3) ; CHECK-WACC-NEXT: # implicit-def: $wacc0 ; CHECK-WACC-NEXT: bc 12, 20, L..BB0_2 ; CHECK-WACC-NEXT: # %bb.1: # %bb10 ; CHECK-WACC-NEXT: xvf64gerpp 0, 34, 0 ; CHECK-WACC-NEXT: L..BB0_2: # %bb12 ; CHECK-WACC-NEXT: cmpdi 3, 0 ; CHECK-WACC-NEXT: .align 4 ; CHECK-WACC-NEXT: L..BB0_3: # %bb13 ; CHECK-WACC-NEXT: # ; CHECK-WACC-NEXT: bc 4, 2, L..BB0_3 ; CHECK-WACC-NEXT: # %bb.4: # %bb14 ; CHECK-WACC-NEXT: dmxxextfdmr512 34, 36, 0, 0 ; CHECK-WACC-NEXT: xxlxor 0, 0, 0 ; CHECK-WACC-NEXT: xvsubdp 1, 0, 35 ; CHECK-WACC-NEXT: xxlxor 2, 2, 2 ; CHECK-WACC-NEXT: xvmaddadp 2, 1, 2 ; CHECK-WACC-NEXT: xvadddp 0, 2, 0 ; CHECK-WACC-NEXT: xxswapd 0, 0 ; CHECK-WACC-NEXT: stxv 0, 0(3) ; CHECK-WACC-NEXT: blr bb: %call = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> poison) %extractvalue = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %call, 0 %extractvalue1 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %call, 2 %extractvalue2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %call, 3 %bitcast = bitcast <16 x i8> %extractvalue to <2 x double> %bitcast3 = bitcast <16 x i8> %extractvalue1 to <2 x double> %shufflevector = shufflevector <2 x double> %bitcast, <2 x double> %bitcast3, <2 x i32> %shufflevector4 = shufflevector <2 x double> %shufflevector, <2 x double> poison, <4 x i32> %fneg = fneg <4 x double> %shufflevector4 %shufflevector5 = shufflevector <4 x double> %fneg, <4 x double> poison, <4 x i32> %shufflevector6 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %extractvalue2, <32 x i32> %bitcast7 = bitcast <32 x i8> %shufflevector6 to <4 x double> %fsub = fsub <4 x double> %shufflevector5, %bitcast7 %shufflevector8 = shufflevector <4 x double> poison, <4 x double> %fsub, <4 x i32> %fmul = fmul <4 x double> %shufflevector8, zeroinitializer %call9 = tail call <4 x double> @llvm.fmuladd.v4f64(<4 x double> zeroinitializer, <4 x double> zeroinitializer, <4 x double> %fmul) %fadd = fadd <4 x double> %call9, zeroinitializer store <4 x double> %fadd, ptr poison, align 4 br i1 poison, label %bb10, label %bb12 bb10: ; preds = %bb %call11 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> poison, <256 x i1> poison, <16 x i8> poison) br label %bb12 bb12: ; preds = %bb10, %bb %phi = phi <512 x i1> [ poison, %bb ], [ %call11, %bb10 ] br label %bb13 bb13: ; preds = %bb13, %bb12 %icmp = icmp eq i64 0, %arg br i1 %icmp, label %bb14, label %bb13 bb14: ; preds = %bb13 %call15 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> poison) %extractvalue16 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %call15, 1 %call17 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %phi) %extractvalue18 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %call17, 1 %bitcast19 = bitcast <16 x i8> %extractvalue16 to <2 x double> %bitcast20 = bitcast <16 x i8> %extractvalue18 to <2 x double> %fsub21 = fsub <2 x double> zeroinitializer, %bitcast19 %fadd22 = fadd <2 x double> zeroinitializer, %fsub21 %fadd23 = fadd <2 x double> %fadd22, zeroinitializer %fsub24 = fsub <2 x double> zeroinitializer, %bitcast20 %fadd25 = fadd <2 x double> zeroinitializer, %fsub24 %fadd26 = fadd <2 x double> %fadd25, zeroinitializer %fadd27 = fadd <2 x double> %fadd26, zeroinitializer %call28 = tail call <2 x double> @llvm.fmuladd.v2f64(<2 x double> %fadd27, <2 x double> zeroinitializer, <2 x double> zeroinitializer) %fadd29 = fadd <2 x double> zeroinitializer, %call28 %shufflevector30 = shufflevector <2 x double> %fadd29, <2 x double> poison, <2 x i32> store <2 x double> %shufflevector30, ptr poison, align 4 ret void } ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) declare <512 x i1> @llvm.ppc.mma.xxsetaccz() #1 ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) declare <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>) #1 ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>) #1 ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) declare double @llvm.fmuladd.f64(double, double, double) #2 ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) declare <2 x double> @llvm.fmuladd.v2f64(<2 x double>, <2 x double>, <2 x double>) #2 ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) declare <4 x double> @llvm.fmuladd.v4f64(<4 x double>, <4 x double>, <4 x double>) #2 attributes #0 = { "target-features"="+altivec,+bpermd,+crbits,+crypto,+direct-move,+extdiv,+isa-v206-instructions,+isa-v207-instructions,+isa-v30-instructions,+isa-v31-instructions,+mma,+paired-vector-memops,+pcrelative-memops,+power10-vector,+power8-vector,+power9-vector,+prefix-instrs,+quadword-atomics,+vsx,-aix-shared-lib-tls-model-opt,-aix-small-local-dynamic-tls,-aix-small-local-exec-tls,-htm,-privileged,-rop-protect,-spe" } attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }