; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -verify-machineinstrs -mcpu=pwr10 \
; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=future \
; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck -check-prefix=FUTURE %s

; RUN: llc -verify-machineinstrs -mcpu=pwr10 \
; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=future \
; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck --check-prefix=FUTURE %s

; Function Attrs: nounwind readnone
define void @stxvl1(<16 x i8> %a, ptr %b, i64 %c) {
; CHECK-LABEL: stxvl1:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    sldi 3, 6, 56
; CHECK-NEXT:    stxvl 34, 5, 3
; CHECK-NEXT:    blr
;
; FUTURE-LABEL: stxvl1:
; FUTURE:       # %bb.0: # %entry
; FUTURE-NEXT:    stxvrl 34, 5, 6
; FUTURE-NEXT:    blr
entry:
  %cconv =  trunc i64 %c to i32
  tail call void @llvm.vp.store.v16i8.p0(<16 x i8> %a, ptr %b, <16 x i1> splat (i1 true), i32 %cconv)
  ret void
}

; Function Attrs: nounwind readnone
define void @stxvl2(<8 x i16> %a, ptr %b, i64 %c) {
; CHECK-LABEL: stxvl2:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    sldi 3, 6, 57
; CHECK-NEXT:    stxvl 34, 5, 3
; CHECK-NEXT:    blr
;
; FUTURE-LABEL: stxvl2:
; FUTURE:       # %bb.0: # %entry
; FUTURE-NEXT:    sldi 3, 6, 1
; FUTURE-NEXT:    stxvrl 34, 5, 3
; FUTURE-NEXT:    blr
entry:
  %cconv =  trunc i64 %c to i32
  tail call void @llvm.vp.store.v8i16.p0(<8 x i16> %a, ptr %b, <8 x i1> splat (i1 true), i32 %cconv)
  ret void
}

; Function Attrs: nounwind readnone
define void @stxvl4(<4 x i32> %a, ptr %b, i64 %c) {
; CHECK-LABEL: stxvl4:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    sldi 3, 6, 58
; CHECK-NEXT:    stxvl 34, 5, 3
; CHECK-NEXT:    blr
;
; FUTURE-LABEL: stxvl4:
; FUTURE:       # %bb.0: # %entry
; FUTURE-NEXT:    sldi 3, 6, 2
; FUTURE-NEXT:    stxvrl 34, 5, 3
; FUTURE-NEXT:    blr
entry:
  %cconv =  trunc i64 %c to i32
  tail call void @llvm.vp.store.v4i32.p0(<4 x i32> %a, ptr %b, <4 x i1> splat (i1 true), i32 %cconv)
  ret void
}

; Function Attrs: nounwind readnone
define void @stxvl8(<2 x i64> %a, ptr %b, i64 %c) {
; CHECK-LABEL: stxvl8:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    sldi 3, 6, 59
; CHECK-NEXT:    stxvl 34, 5, 3
; CHECK-NEXT:    blr
;
; FUTURE-LABEL: stxvl8:
; FUTURE:       # %bb.0: # %entry
; FUTURE-NEXT:    sldi 3, 6, 3
; FUTURE-NEXT:    stxvrl 34, 5, 3
; FUTURE-NEXT:    blr
entry:
  %cconv =  trunc i64 %c to i32
  tail call void @llvm.vp.store.v2i64.p0(<2 x i64> %a, ptr %b, <2 x i1> splat (i1 true), i32 %cconv)
  ret void
}

; Function Attrs: nounwind readnone
define <16 x i8> @lxvl1(ptr %a, i64 %b) {
; CHECK-LABEL: lxvl1:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    sldi 4, 4, 56
; CHECK-NEXT:    lxvl 34, 3, 4
; CHECK-NEXT:    blr
;
; FUTURE-LABEL: lxvl1:
; FUTURE:       # %bb.0: # %entry
; FUTURE-NEXT:    lxvrl 34, 3, 4
; FUTURE-NEXT:    blr
entry:
  %bconv =  trunc i64 %b to i32
  %0 = tail call <16 x i8> @llvm.vp.load.v16i8.p0(ptr %a, <16 x i1> splat (i1 true), i32 %bconv)
  ret <16 x i8> %0
}

; Function Attrs: nounwind readnone
define <8 x i16> @lxvl2(ptr %a, i64 %b) {
; CHECK-LABEL: lxvl2:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    sldi 4, 4, 57
; CHECK-NEXT:    lxvl 34, 3, 4
; CHECK-NEXT:    blr
;
; FUTURE-LABEL: lxvl2:
; FUTURE:       # %bb.0: # %entry
; FUTURE-NEXT:    sldi 4, 4, 1
; FUTURE-NEXT:    lxvrl 34, 3, 4
; FUTURE-NEXT:    blr
entry:
  %bconv =  trunc i64 %b to i32
  %0 = tail call <8 x i16> @llvm.vp.load.v8i16.p0(ptr %a, <8 x i1> splat (i1 true), i32 %bconv)
  ret <8 x i16> %0
}

; Function Attrs: nounwind readnone
define <4 x i32> @lxvl4(ptr %a, i64 %b) {
; CHECK-LABEL: lxvl4:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    sldi 4, 4, 58
; CHECK-NEXT:    lxvl 34, 3, 4
; CHECK-NEXT:    blr
;
; FUTURE-LABEL: lxvl4:
; FUTURE:       # %bb.0: # %entry
; FUTURE-NEXT:    sldi 4, 4, 2
; FUTURE-NEXT:    lxvrl 34, 3, 4
; FUTURE-NEXT:    blr
entry:
  %bconv =  trunc i64 %b to i32
  %0 = tail call <4 x i32> @llvm.vp.load.v4i32.p0(ptr %a, <4 x i1> splat (i1 true), i32 %bconv)
  ret <4 x i32> %0
}

; Function Attrs: nounwind readnone
define <2 x i64> @lxvl8(ptr %a, i64 %b) {
; CHECK-LABEL: lxvl8:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    sldi 4, 4, 59
; CHECK-NEXT:    lxvl 34, 3, 4
; CHECK-NEXT:    blr
;
; FUTURE-LABEL: lxvl8:
; FUTURE:       # %bb.0: # %entry
; FUTURE-NEXT:    sldi 4, 4, 3
; FUTURE-NEXT:    lxvrl 34, 3, 4
; FUTURE-NEXT:    blr
entry:
  %bconv =  trunc i64 %b to i32
  %0 = tail call <2 x i64> @llvm.vp.load.v2i64.p0(ptr %a, <2 x i1> splat (i1 true), i32 %bconv)
  ret <2 x i64> %0
}