; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=riscv32 -mattr=+zbkb -global-isel \
; RUN:   -global-isel-abort=1 -verify-machineinstrs < %s \
; RUN:   | FileCheck %s --check-prefix=RV32ZBKB
; RUN: llc -mtriple=riscv64 -mattr=+zbkb -global-isel \
; RUN:   -global-isel-abort=1 -verify-machineinstrs < %s \
; RUN:   | FileCheck %s --check-prefix=RV64ZBKB

; RUN: llc -mtriple=riscv32 -global-isel \
; RUN:   -global-isel-abort=1 -verify-machineinstrs < %s \
; RUN:   | FileCheck %s --check-prefix=RV32NOZBKB
; RUN: llc -mtriple=riscv64 -global-isel \
; RUN:   -global-isel-abort=1 -verify-machineinstrs < %s \
; RUN:   | FileCheck %s --check-prefix=RV64NOZBKB

declare i8 @llvm.bitreverse.i8(i8)

define zeroext i8 @bitreverse_i8_zext_arg(i8 zeroext %x) {
; RV32ZBKB-LABEL: bitreverse_i8_zext_arg:
; RV32ZBKB:       # %bb.0:
; RV32ZBKB-NEXT:    brev8 a0, a0
; RV32ZBKB-NEXT:    ret
;
; RV64ZBKB-LABEL: bitreverse_i8_zext_arg:
; RV64ZBKB:       # %bb.0:
; RV64ZBKB-NEXT:    brev8 a0, a0
; RV64ZBKB-NEXT:    ret
;
; RV32NOZBKB-LABEL: bitreverse_i8_zext_arg:
; RV32NOZBKB:       # %bb.0:
; RV32NOZBKB-NEXT:    andi a1, a0, -16
; RV32NOZBKB-NEXT:    slli a0, a0, 4
; RV32NOZBKB-NEXT:    srli a1, a1, 4
; RV32NOZBKB-NEXT:    or a0, a1, a0
; RV32NOZBKB-NEXT:    andi a1, a0, -52
; RV32NOZBKB-NEXT:    slli a0, a0, 2
; RV32NOZBKB-NEXT:    zext.b a1, a1
; RV32NOZBKB-NEXT:    andi a0, a0, -52
; RV32NOZBKB-NEXT:    srli a1, a1, 2
; RV32NOZBKB-NEXT:    or a0, a1, a0
; RV32NOZBKB-NEXT:    andi a1, a0, -86
; RV32NOZBKB-NEXT:    slli a0, a0, 1
; RV32NOZBKB-NEXT:    zext.b a1, a1
; RV32NOZBKB-NEXT:    srli a1, a1, 1
; RV32NOZBKB-NEXT:    andi a0, a0, -86
; RV32NOZBKB-NEXT:    or a0, a1, a0
; RV32NOZBKB-NEXT:    zext.b a0, a0
; RV32NOZBKB-NEXT:    ret
;
; RV64NOZBKB-LABEL: bitreverse_i8_zext_arg:
; RV64NOZBKB:       # %bb.0:
; RV64NOZBKB-NEXT:    andi a1, a0, -16
; RV64NOZBKB-NEXT:    slli a0, a0, 4
; RV64NOZBKB-NEXT:    srli a1, a1, 4
; RV64NOZBKB-NEXT:    or a0, a1, a0
; RV64NOZBKB-NEXT:    andi a1, a0, -52
; RV64NOZBKB-NEXT:    slli a0, a0, 2
; RV64NOZBKB-NEXT:    zext.b a1, a1
; RV64NOZBKB-NEXT:    andi a0, a0, -52
; RV64NOZBKB-NEXT:    srli a1, a1, 2
; RV64NOZBKB-NEXT:    or a0, a1, a0
; RV64NOZBKB-NEXT:    andi a1, a0, -86
; RV64NOZBKB-NEXT:    slli a0, a0, 1
; RV64NOZBKB-NEXT:    zext.b a1, a1
; RV64NOZBKB-NEXT:    srli a1, a1, 1
; RV64NOZBKB-NEXT:    andi a0, a0, -86
; RV64NOZBKB-NEXT:    or a0, a1, a0
; RV64NOZBKB-NEXT:    zext.b a0, a0
; RV64NOZBKB-NEXT:    ret
  %r = call i8 @llvm.bitreverse.i8(i8 %x)
  ret i8 %r
}

define zeroext i8 @bitreverse_i8_plain_arg(i8 %x) {
; RV32ZBKB-LABEL: bitreverse_i8_plain_arg:
; RV32ZBKB:       # %bb.0:
; RV32ZBKB-NEXT:    brev8 a0, a0
; RV32ZBKB-NEXT:    zext.b a0, a0
; RV32ZBKB-NEXT:    ret
;
; RV64ZBKB-LABEL: bitreverse_i8_plain_arg:
; RV64ZBKB:       # %bb.0:
; RV64ZBKB-NEXT:    brev8 a0, a0
; RV64ZBKB-NEXT:    zext.b a0, a0
; RV64ZBKB-NEXT:    ret
;
; RV32NOZBKB-LABEL: bitreverse_i8_plain_arg:
; RV32NOZBKB:       # %bb.0:
; RV32NOZBKB-NEXT:    zext.b a1, a0
; RV32NOZBKB-NEXT:    or a0, a1, a0
; RV32NOZBKB-NEXT:    andi a1, a0, -16
; RV32NOZBKB-NEXT:    slli a0, a0, 4
; RV32NOZBKB-NEXT:    zext.b a1, a1
; RV32NOZBKB-NEXT:    srli a1, a1, 4
; RV32NOZBKB-NEXT:    or a0, a1, a0
; RV32NOZBKB-NEXT:    andi a1, a0, -52
; RV32NOZBKB-NEXT:    slli a0, a0, 2
; RV32NOZBKB-NEXT:    zext.b a1, a1
; RV32NOZBKB-NEXT:    andi a0, a0, -52
; RV32NOZBKB-NEXT:    srli a1, a1, 2
; RV32NOZBKB-NEXT:    or a0, a1, a0
; RV32NOZBKB-NEXT:    andi a1, a0, -86
; RV32NOZBKB-NEXT:    slli a0, a0, 1
; RV32NOZBKB-NEXT:    zext.b a1, a1
; RV32NOZBKB-NEXT:    srli a1, a1, 1
; RV32NOZBKB-NEXT:    andi a0, a0, -86
; RV32NOZBKB-NEXT:    or a0, a1, a0
; RV32NOZBKB-NEXT:    zext.b a0, a0
; RV32NOZBKB-NEXT:    ret
;
; RV64NOZBKB-LABEL: bitreverse_i8_plain_arg:
; RV64NOZBKB:       # %bb.0:
; RV64NOZBKB-NEXT:    zext.b a1, a0
; RV64NOZBKB-NEXT:    or a0, a1, a0
; RV64NOZBKB-NEXT:    andi a1, a0, -16
; RV64NOZBKB-NEXT:    slli a0, a0, 4
; RV64NOZBKB-NEXT:    zext.b a1, a1
; RV64NOZBKB-NEXT:    srli a1, a1, 4
; RV64NOZBKB-NEXT:    or a0, a1, a0
; RV64NOZBKB-NEXT:    andi a1, a0, -52
; RV64NOZBKB-NEXT:    slli a0, a0, 2
; RV64NOZBKB-NEXT:    zext.b a1, a1
; RV64NOZBKB-NEXT:    andi a0, a0, -52
; RV64NOZBKB-NEXT:    srli a1, a1, 2
; RV64NOZBKB-NEXT:    or a0, a1, a0
; RV64NOZBKB-NEXT:    andi a1, a0, -86
; RV64NOZBKB-NEXT:    slli a0, a0, 1
; RV64NOZBKB-NEXT:    zext.b a1, a1
; RV64NOZBKB-NEXT:    srli a1, a1, 1
; RV64NOZBKB-NEXT:    andi a0, a0, -86
; RV64NOZBKB-NEXT:    or a0, a1, a0
; RV64NOZBKB-NEXT:    zext.b a0, a0
; RV64NOZBKB-NEXT:    ret
  %r = call i8 @llvm.bitreverse.i8(i8 %x)
  ret i8 %r
}