# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+zfh,+d -run-pass=instruction-select \
# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=riscv64 -mattr=+zfh,+d -run-pass=instruction-select \
# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s

---
name:            fadd_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fadd_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FADD_H:%[0-9]+]]:fpr16 = nofpexcept FADD_H [[COPY]], [[COPY1]], 7
    ; CHECK-NEXT: $f10_h = COPY [[FADD_H]]
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %2:fprb(s16) = G_FADD %0, %1
    $f10_h = COPY %2(s16)
    PseudoRET implicit $f10_h

...
---
name:            fsub_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fsub_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FSUB_H:%[0-9]+]]:fpr16 = nofpexcept FSUB_H [[COPY]], [[COPY1]], 7
    ; CHECK-NEXT: $f10_h = COPY [[FSUB_H]]
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %2:fprb(s16) = G_FSUB %0, %1
    $f10_h = COPY %2(s16)
    PseudoRET implicit $f10_h

...
---
name:            fmul_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fmul_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FMUL_H:%[0-9]+]]:fpr16 = nofpexcept FMUL_H [[COPY]], [[COPY1]], 7
    ; CHECK-NEXT: $f10_h = COPY [[FMUL_H]]
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %2:fprb(s16) = G_FMUL %0, %1
    $f10_h = COPY %2(s16)
    PseudoRET implicit $f10_h

...
---
name:            fdiv_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fdiv_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FDIV_H:%[0-9]+]]:fpr16 = nofpexcept FDIV_H [[COPY]], [[COPY1]], 7
    ; CHECK-NEXT: $f10_h = COPY [[FDIV_H]]
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %2:fprb(s16) = G_FDIV %0, %1
    $f10_h = COPY %2(s16)
    PseudoRET implicit $f10_h

...
---
name:            fma_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_h, $f12_h

    ; CHECK-LABEL: name: fma_f16
    ; CHECK: liveins: $f10_h, $f11_h, $f12_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY $f12_h
    ; CHECK-NEXT: [[FMADD_H:%[0-9]+]]:fpr16 = nofpexcept FMADD_H [[COPY]], [[COPY1]], [[COPY2]], 7
    ; CHECK-NEXT: $f10_h = COPY [[FMADD_H]]
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %2:fprb(s16) = COPY $f12_h
    %3:fprb(s16) = G_FMA %0, %1, %2
    $f10_h = COPY %3(s16)
    PseudoRET implicit $f10_h

...
---
name:            fneg_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_h, $f12_h

    ; CHECK-LABEL: name: fneg_f16
    ; CHECK: liveins: $f10_h, $f11_h, $f12_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[FSGNJN_H:%[0-9]+]]:fpr16 = FSGNJN_H [[COPY]], [[COPY]]
    ; CHECK-NEXT: $f10_h = COPY [[FSGNJN_H]]
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = G_FNEG %0
    $f10_h = COPY %1(s16)
    PseudoRET implicit $f10_h

...
---
name:            fabs_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_h, $f12_h

    ; CHECK-LABEL: name: fabs_f16
    ; CHECK: liveins: $f10_h, $f11_h, $f12_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[FSGNJX_H:%[0-9]+]]:fpr16 = FSGNJX_H [[COPY]], [[COPY]]
    ; CHECK-NEXT: $f10_h = COPY [[FSGNJX_H]]
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = G_FABS %0
    $f10_h = COPY %1(s16)
    PseudoRET implicit $f10_h

...
---
name:            fsqrt_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_h, $f12_h

    ; CHECK-LABEL: name: fsqrt_f16
    ; CHECK: liveins: $f10_h, $f11_h, $f12_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[FSQRT_H:%[0-9]+]]:fpr16 = nofpexcept FSQRT_H [[COPY]], 7
    ; CHECK-NEXT: $f10_h = COPY [[FSQRT_H]]
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = G_FSQRT %0
    $f10_h = COPY %1(s16)
    PseudoRET implicit $f10_h

...
---
name:            fmaxnum_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fmaxnum_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FMAX_H:%[0-9]+]]:fpr16 = nofpexcept FMAX_H [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $f10_h = COPY [[FMAX_H]]
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %2:fprb(s16) = G_FMAXNUM %0, %1
    $f10_h = COPY %2(s16)
    PseudoRET implicit $f10_h

...
---
name:            fminnum_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fminnum_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FMIN_H:%[0-9]+]]:fpr16 = nofpexcept FMIN_H [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $f10_h = COPY [[FMIN_H]]
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %2:fprb(s16) = G_FMINNUM %0, %1
    $f10_h = COPY %2(s16)
    PseudoRET implicit $f10_h

...
---
name:            fcopysign_f16_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fcopysign_f16_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FSGNJ_H:%[0-9]+]]:fpr16 = FSGNJ_H [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $f10_h = COPY [[FSGNJ_H]]
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %2:fprb(s16) = G_FCOPYSIGN %0, %1
    $f10_h = COPY %2(s16)
    PseudoRET implicit $f10_h

...
---
name:            fcopysign_f16_f32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_f

    ; CHECK-LABEL: name: fcopysign_f16_f32
    ; CHECK: liveins: $f10_h, $f11_f
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
    ; CHECK-NEXT: [[FCVT_H_S:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_S [[COPY1]], 7
    ; CHECK-NEXT: [[FSGNJ_H:%[0-9]+]]:fpr16 = FSGNJ_H [[COPY]], [[FCVT_H_S]]
    ; CHECK-NEXT: $f10_h = COPY [[FSGNJ_H]]
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s32) = COPY $f11_f
    %2:fprb(s16) = G_FCOPYSIGN %0, %1
    $f10_h = COPY %2(s16)
    PseudoRET implicit $f10_h

...
---
name:            fcopysign_f32_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_f, $f11_h

    ; CHECK-LABEL: name: fcopysign_f32_f16
    ; CHECK: liveins: $f10_f, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FCVT_S_H:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_H [[COPY1]], 0
    ; CHECK-NEXT: [[FSGNJ_S:%[0-9]+]]:fpr32 = FSGNJ_S [[COPY]], [[FCVT_S_H]]
    ; CHECK-NEXT: $f10_f = COPY [[FSGNJ_S]]
    ; CHECK-NEXT: PseudoRET implicit $f10_f
    %0:fprb(s32) = COPY $f10_f
    %1:fprb(s16) = COPY $f11_h
    %2:fprb(s32) = G_FCOPYSIGN %0, %1
    $f10_f = COPY %2(s32)
    PseudoRET implicit $f10_f

...
---
name:            fcopysign_f16_f64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_d

    ; CHECK-LABEL: name: fcopysign_f16_f64
    ; CHECK: liveins: $f10_h, $f11_d
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
    ; CHECK-NEXT: [[FCVT_H_D:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_D [[COPY1]], 7
    ; CHECK-NEXT: [[FSGNJ_H:%[0-9]+]]:fpr16 = FSGNJ_H [[COPY]], [[FCVT_H_D]]
    ; CHECK-NEXT: $f10_h = COPY [[FSGNJ_H]]
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s64) = COPY $f11_d
    %2:fprb(s16) = G_FCOPYSIGN %0, %1
    $f10_h = COPY %2(s16)
    PseudoRET implicit $f10_h

...
---
name:            fcopysign_f64_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_d, $f11_h

    ; CHECK-LABEL: name: fcopysign_f64_f16
    ; CHECK: liveins: $f10_d, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FCVT_D_H:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_H [[COPY1]], 0
    ; CHECK-NEXT: [[FSGNJ_D:%[0-9]+]]:fpr64 = FSGNJ_D [[COPY]], [[FCVT_D_H]]
    ; CHECK-NEXT: $f10_d = COPY [[FSGNJ_D]]
    ; CHECK-NEXT: PseudoRET implicit $f10_d
    %0:fprb(s64) = COPY $f10_d
    %1:fprb(s16) = COPY $f11_h
    %2:fprb(s64) = G_FCOPYSIGN %0, %1
    $f10_d = COPY %2(s64)
    PseudoRET implicit $f10_d

...