# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -verify-machineinstrs -mattr='+zba' %s -o - | FileCheck %s --check-prefix=ZBA
---
name:            zext_32_64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: zext_32_64
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 32
    ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[SLLI]], 32
    ; CHECK-NEXT: $x8 = COPY [[SRLI]]
    ;
    ; ZBA-LABEL: name: zext_32_64
    ; ZBA: liveins: $x10
    ; ZBA-NEXT: {{  $}}
    ; ZBA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; ZBA-NEXT: [[ADD_UW:%[0-9]+]]:gpr = ADD_UW [[COPY]], $x0
    ; ZBA-NEXT: $x8 = COPY [[ADD_UW]]
    %0:gprb(s64) = COPY $x10
    %1:gprb(s32) = G_TRUNC %0
    %2:gprb(s64) = G_ZEXT %1
    $x8 = COPY %2(s64)
...