; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=CHECK,RV64

define i1 @test1(i64 %x) {
; RV32-LABEL: test1:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a2, a1, 2
; RV32-NEXT:    srli a0, a0, 30
; RV32-NEXT:    srai a1, a1, 30
; RV32-NEXT:    or a0, a0, a2
; RV32-NEXT:    xori a0, a0, -2
; RV32-NEXT:    not a1, a1
; RV32-NEXT:    or a0, a0, a1
; RV32-NEXT:    seqz a0, a0
; RV32-NEXT:    ret
;
; RV64-LABEL: test1:
; RV64:       # %bb.0:
; RV64-NEXT:    srai a0, a0, 30
; RV64-NEXT:    addi a0, a0, 2
; RV64-NEXT:    seqz a0, a0
; RV64-NEXT:    ret
  %a = and i64 %x, -1073741824
  %b = icmp eq i64 %a, -2147483648
  ret i1 %b
}

define i1 @test2(i32 signext %x) {
; CHECK-LABEL: test2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    srli a0, a0, 30
; CHECK-NEXT:    seqz a0, a0
; CHECK-NEXT:    ret
  %a = and i32 %x, -1073741824
  %b = icmp eq i32 %a, 0
  ret i1 %b
}

define i1 @test3(i32 signext %x) {
; CHECK-LABEL: test3:
; CHECK:       # %bb.0:
; CHECK-NEXT:    srli a0, a0, 29
; CHECK-NEXT:    snez a0, a0
; CHECK-NEXT:    ret
  %a = and i32 %x, -536870912
  %b = icmp ne i32 %a, 0
  ret i1 %b
}

define i1 @test4(i64 %x) {
; RV32-LABEL: test4:
; RV32:       # %bb.0:
; RV32-NEXT:    srli a1, a1, 14
; RV32-NEXT:    seqz a0, a1
; RV32-NEXT:    ret
;
; RV64-LABEL: test4:
; RV64:       # %bb.0:
; RV64-NEXT:    srli a0, a0, 46
; RV64-NEXT:    seqz a0, a0
; RV64-NEXT:    ret
  %a = and i64 %x, -70368744177664
  %b = icmp eq i64 %a, 0
  ret i1 %b
}

define i1 @test5(i64 %x) {
; RV32-LABEL: test5:
; RV32:       # %bb.0:
; RV32-NEXT:    srli a0, a0, 29
; RV32-NEXT:    seqz a0, a0
; RV32-NEXT:    ret
;
; RV64-LABEL: test5:
; RV64:       # %bb.0:
; RV64-NEXT:    sraiw a0, a0, 29
; RV64-NEXT:    seqz a0, a0
; RV64-NEXT:    ret
  %a = and i64 %x, u0xE0000000
  %b = icmp eq i64 %a, 0
  ret i1 %b
}

define i1 @test6(i64 %x) {
; RV32-LABEL: test6:
; RV32:       # %bb.0:
; RV32-NEXT:    srli a0, a0, 29
; RV32-NEXT:    snez a0, a0
; RV32-NEXT:    ret
;
; RV64-LABEL: test6:
; RV64:       # %bb.0:
; RV64-NEXT:    sraiw a0, a0, 29
; RV64-NEXT:    snez a0, a0
; RV64-NEXT:    ret
  %a = and i64 %x, u0xE0000000
  %b = icmp ne i64 %a, 0
  ret i1 %b
}

define i1 @test7(i64 %x) {
; RV32-LABEL: test7:
; RV32:       # %bb.0:
; RV32-NEXT:    srli a0, a0, 29
; RV32-NEXT:    addi a0, a0, -6
; RV32-NEXT:    seqz a0, a0
; RV32-NEXT:    ret
;
; RV64-LABEL: test7:
; RV64:       # %bb.0:
; RV64-NEXT:    sraiw a0, a0, 29
; RV64-NEXT:    addi a0, a0, 2
; RV64-NEXT:    seqz a0, a0
; RV64-NEXT:    ret
  %a = and i64 %x, u0xE0000000
  %b = icmp eq i64 %a, u0xC0000000
  ret i1 %b
}

define i1 @test8(i64 %x) {
; RV32-LABEL: test8:
; RV32:       # %bb.0:
; RV32-NEXT:    srai a0, a0, 20
; RV32-NEXT:    xori a0, a0, -2048
; RV32-NEXT:    snez a0, a0
; RV32-NEXT:    ret
;
; RV64-LABEL: test8:
; RV64:       # %bb.0:
; RV64-NEXT:    sraiw a0, a0, 20
; RV64-NEXT:    xori a0, a0, -2048
; RV64-NEXT:    snez a0, a0
; RV64-NEXT:    ret
  %a = and i64 %x, u0xFFF00000
  %b = icmp ne i64 %a, u0x80000000
  ret i1 %b
}

define i1 @test9(i64 %x) {
; RV32-LABEL: test9:
; RV32:       # %bb.0:
; RV32-NEXT:    srli a0, a0, 16
; RV32-NEXT:    addi a0, a0, -2048
; RV32-NEXT:    seqz a0, a0
; RV32-NEXT:    ret
;
; RV64-LABEL: test9:
; RV64:       # %bb.0:
; RV64-NEXT:    sraiw a0, a0, 16
; RV64-NEXT:    addi a0, a0, -2048
; RV64-NEXT:    seqz a0, a0
; RV64-NEXT:    ret
  %a = and i64 %x, u0xFFFF0000
  %b = icmp eq i64 %a, u0x08000000
  ret i1 %b
}

; Make sure the and constant doesn't get converted to an opaque constant by
; ConstantHoisting. If it's an opaque constant, we'll have addi -16 and addi 15.
define i64 @test10(i64 %0) #0 {
; RV32-LABEL: test10:
; RV32:       # %bb.0: # %entry
; RV32-NEXT:    addi a0, a0, -1
; RV32-NEXT:    andi a0, a0, -16
; RV32-NEXT:    snez a0, a0
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    ret
;
; RV64-LABEL: test10:
; RV64:       # %bb.0: # %entry
; RV64-NEXT:    addi a0, a0, -1
; RV64-NEXT:    sraiw a0, a0, 4
; RV64-NEXT:    snez a0, a0
; RV64-NEXT:    ret
entry:
  %1 = add nuw nsw i64 %0, u0xffffffff
  %2 = and i64 %1, u0xfffffff0
  %3 = icmp ne i64 %2, 0
  %4 = zext i1 %3 to i64
  ret i64 %4
}

; Make sure the and constant doesn't get converted to an opaque constant by
; ConstantHoisting. If it's an opaque constant, we'll have addi -16 and addi 15.
define i64 @test11(i64 %0) #0 {
; RV32-LABEL: test11:
; RV32:       # %bb.0: # %entry
; RV32-NEXT:    addi a0, a0, -1
; RV32-NEXT:    srai a0, a0, 4
; RV32-NEXT:    addi a0, a0, 1621
; RV32-NEXT:    seqz a0, a0
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    ret
;
; RV64-LABEL: test11:
; RV64:       # %bb.0: # %entry
; RV64-NEXT:    addi a0, a0, -1
; RV64-NEXT:    sraiw a0, a0, 4
; RV64-NEXT:    addi a0, a0, 1621
; RV64-NEXT:    seqz a0, a0
; RV64-NEXT:    ret
entry:
  %1 = add nuw nsw i64 %0, u0xffffffff
  %2 = and i64 %1, u0xfffffff0
  %3 = icmp eq i64 %2, u0xffff9ab0
  %4 = zext i1 %3 to i64
  ret i64 %4
}

; Make sure the and constant doesn't get converted to an opaque constant by
; ConstantHoisting. If it's an opaque constant we'll end up with constant
; materialization sequences on RV64.
define i64 @test12(i64 %0) #0 {
; RV32-LABEL: test12:
; RV32:       # %bb.0: # %entry
; RV32-NEXT:    addi a0, a0, -3
; RV32-NEXT:    seqz a0, a0
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    ret
;
; RV64-LABEL: test12:
; RV64:       # %bb.0: # %entry
; RV64-NEXT:    addi a0, a0, -16
; RV64-NEXT:    addiw a0, a0, 13
; RV64-NEXT:    seqz a0, a0
; RV64-NEXT:    ret
entry:
  %1 = add nuw nsw i64 %0, u0xfffffff0
  %2 = and i64 %1, u0xffffffff
  %3 = icmp eq i64 %2, u0xfffffff3
  %4 = zext i1 %3 to i64
  ret i64 %4
}

; Make sure the and constant doesn't get converted to an opaque constant by
; ConstantHoisting.
define i64 @test13(i64 %0) #0 {
; RV32-LABEL: test13:
; RV32:       # %bb.0: # %entry
; RV32-NEXT:    lui a1, 524288
; RV32-NEXT:    addi a1, a1, 15
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    srli a0, a0, 31
; RV32-NEXT:    seqz a0, a0
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    ret
;
; RV64-LABEL: test13:
; RV64:       # %bb.0: # %entry
; RV64-NEXT:    lui a1, 524288
; RV64-NEXT:    addi a1, a1, -15
; RV64-NEXT:    sub a0, a0, a1
; RV64-NEXT:    sraiw a0, a0, 31
; RV64-NEXT:    seqz a0, a0
; RV64-NEXT:    ret
entry:
  %1 = add nuw nsw i64 %0, u0x8000000f
  %2 = and i64 %1, u0x80000000
  %3 = icmp eq i64 %2, 0
  %4 = zext i1 %3 to i64
  ret i64 %4
}