; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -target-abi=ilp32 -mattr=+d -verify-machineinstrs < %s | FileCheck -check-prefix=RV32IFD-LE %s
; RUN: llc -mtriple=riscv32be -target-abi=ilp32 -mattr=+d -verify-machineinstrs < %s | FileCheck -check-prefix=RV32IFD-BE %s

; Test operations that involve SplitF64/BuildPairF64 on RV32 with D extension
; but soft-float ABI. This configuration triggers the special handling for
; big-endian.

define double @fneg(double %a) nounwind {
; RV32IFD-LE-LABEL: fneg:
; RV32IFD-LE:       # %bb.0:
; RV32IFD-LE-NEXT:    lui a2, 524288
; RV32IFD-LE-NEXT:    xor a1, a1, a2
; RV32IFD-LE-NEXT:    ret
;
; RV32IFD-BE-LABEL: fneg:
; RV32IFD-BE:       # %bb.0:
; RV32IFD-BE-NEXT:    lui a2, 524288
; RV32IFD-BE-NEXT:    xor a0, a0, a2
; RV32IFD-BE-NEXT:    ret
  %1 = fneg double %a
  ret double %1
}

define double @fabs(double %a) nounwind {
; RV32IFD-LE-LABEL: fabs:
; RV32IFD-LE:       # %bb.0:
; RV32IFD-LE-NEXT:    slli a1, a1, 1
; RV32IFD-LE-NEXT:    srli a1, a1, 1
; RV32IFD-LE-NEXT:    ret
;
; RV32IFD-BE-LABEL: fabs:
; RV32IFD-BE:       # %bb.0:
; RV32IFD-BE-NEXT:    slli a0, a0, 1
; RV32IFD-BE-NEXT:    srli a0, a0, 1
; RV32IFD-BE-NEXT:    ret
  %1 = call double @llvm.fabs.f64(double %a)
  ret double %1
}

define double @fcopysign(double %a, double %b) nounwind {
; RV32IFD-LE-LABEL: fcopysign:
; RV32IFD-LE:       # %bb.0:
; RV32IFD-LE-NEXT:    addi sp, sp, -16
; RV32IFD-LE-NEXT:    sw a2, 8(sp)
; RV32IFD-LE-NEXT:    sw a3, 12(sp)
; RV32IFD-LE-NEXT:    fld fa5, 8(sp)
; RV32IFD-LE-NEXT:    sw a0, 8(sp)
; RV32IFD-LE-NEXT:    sw a1, 12(sp)
; RV32IFD-LE-NEXT:    fld fa4, 8(sp)
; RV32IFD-LE-NEXT:    fsgnj.d fa5, fa4, fa5
; RV32IFD-LE-NEXT:    fsd fa5, 8(sp)
; RV32IFD-LE-NEXT:    lw a0, 8(sp)
; RV32IFD-LE-NEXT:    lw a1, 12(sp)
; RV32IFD-LE-NEXT:    addi sp, sp, 16
; RV32IFD-LE-NEXT:    ret
;
; RV32IFD-BE-LABEL: fcopysign:
; RV32IFD-BE:       # %bb.0:
; RV32IFD-BE-NEXT:    addi sp, sp, -16
; RV32IFD-BE-NEXT:    sw a2, 8(sp)
; RV32IFD-BE-NEXT:    sw a3, 12(sp)
; RV32IFD-BE-NEXT:    fld fa5, 8(sp)
; RV32IFD-BE-NEXT:    sw a0, 8(sp)
; RV32IFD-BE-NEXT:    sw a1, 12(sp)
; RV32IFD-BE-NEXT:    fld fa4, 8(sp)
; RV32IFD-BE-NEXT:    fsgnj.d fa5, fa4, fa5
; RV32IFD-BE-NEXT:    fsd fa5, 8(sp)
; RV32IFD-BE-NEXT:    lw a0, 8(sp)
; RV32IFD-BE-NEXT:    lw a1, 12(sp)
; RV32IFD-BE-NEXT:    addi sp, sp, 16
; RV32IFD-BE-NEXT:    ret
  %1 = call double @llvm.copysign.f64(double %a, double %b)
  ret double %1
}

declare double @llvm.fabs.f64(double)
declare double @llvm.copysign.f64(double, double)