# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 # RUN: llc -mattr=+m -mtriple=riscv64 -run-pass riscv-merge-base-offset %s -o - | FileCheck %s --- | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" target triple = "riscv64" define i64 @udiv64_constant_add(i64 %a) nounwind { %1 = udiv i64 %a, 7 ret i64 %1 } ... --- name: udiv64_constant_add alignment: 4 liveins: - { reg: '$x10', virtual-reg: '' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false hasPatchPoint: false stackSize: 0 offsetAdjustment: 0 maxAlignment: 1 adjustsStack: false hasCalls: false stackProtector: '' functionContext: '' maxCallFrameSize: 0 cvBytesOfCalleeSavedRegisters: 0 hasOpaqueSPAdjustment: false hasVAStart: false hasMustTailInVarArgFunc: false hasTailCall: false isCalleeSavedInfoValid: false localFrameSize: 0 fixedStack: [] stack: [] entry_values: [] callSites: [] debugValueSubstitutions: [] constants: - id: 0 value: i64 2635249153387078803 alignment: 8 isTargetSpecific: false body: | bb.1 (%ir-block.0): liveins: $x10 ; CHECK-LABEL: name: udiv64_constant_add ; CHECK: liveins: $x10 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI target-flags(riscv-hi) %const.0 ; CHECK-NEXT: [[LD:%[0-9]+]]:gpr = LD [[LUI]], target-flags(riscv-lo) %const.0 :: (load (s64) from constant-pool) ; CHECK-NEXT: [[MULHU:%[0-9]+]]:gpr = MULHU [[COPY]], [[LD]] ; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[MULHU]] ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[SUB]], 1 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[SRLI]], [[MULHU]] ; CHECK-NEXT: [[SRLI1:%[0-9]+]]:gpr = SRLI [[ADD]], 2 ; CHECK-NEXT: $x10 = COPY [[SRLI1]] ; CHECK-NEXT: PseudoRET implicit $x10 %0:gpr = COPY $x10 %17:gpr = LUI target-flags(riscv-hi) %const.0 %16:gpr = ADDI %17, target-flags(riscv-lo) %const.0 %4:gpr = LD %16, 0 :: (load (s64) from constant-pool) %8:gpr = MULHU %0, %4 %9:gpr = SUB %0, %8 %11:gpr = SRLI %9, 1 %12:gpr = ADD %11, %8 %13:gpr = SRLI %12, 2 $x10 = COPY %13 PseudoRET implicit $x10 ...