# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+reserve-x6 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs \
# RUN:   -riscv-outliner-regsave=true < %s | FileCheck -check-prefixes=CHECK-X6-RESERVED %s
# RUN: llc -mtriple=riscv32 -mattr=+reserve-x6,+reserve-x7 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs \
# RUN:   -riscv-outliner-regsave=true < %s | FileCheck -check-prefixes=CHECK-X6-X7-RESERVED %s

--- |
  define i32 @outline_x5_live_reserved_0(i32 %a, i32 %b) { ret i32 0 }
  define i32 @outline_x5_live_reserved_1(i32 %a, i32 %b) { ret i32 0 }
  define i32 @outline_x5_live_reserved_2(i32 %a, i32 %b) { ret i32 0 }
...
---
name:            outline_x5_live_reserved_0
tracksRegLiveness: true
body:             |
  ; CHECK-X6-RESERVED-LABEL: name: outline_x5_live_reserved_0
  ; CHECK-X6-RESERVED: bb.0:
  ; CHECK-X6-RESERVED-NEXT:   liveins: $x10, $x11, $x5
  ; CHECK-X6-RESERVED-NEXT: {{  $}}
  ; CHECK-X6-RESERVED-NEXT:   $x7 = ADDI $x5, 0
  ; CHECK-X6-RESERVED-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x7, implicit $x10, implicit $x11
  ; CHECK-X6-RESERVED-NEXT:   $x5 = ADDI $x7, 0
  ; CHECK-X6-RESERVED-NEXT:   PseudoBR %bb.1
  ; CHECK-X6-RESERVED-NEXT: {{  $}}
  ; CHECK-X6-RESERVED-NEXT: bb.1:
  ; CHECK-X6-RESERVED-NEXT:   liveins: $x5, $x14
  ; CHECK-X6-RESERVED-NEXT: {{  $}}
  ; CHECK-X6-RESERVED-NEXT:   $x10 = ADD $x14, $x5
  ; CHECK-X6-RESERVED-NEXT:   PseudoRET implicit $x10
  ;
  ; CHECK-X6-X7-RESERVED-LABEL: name: outline_x5_live_reserved_0
  ; CHECK-X6-X7-RESERVED: bb.0:
  ; CHECK-X6-X7-RESERVED-NEXT:   liveins: $x10, $x11, $x5
  ; CHECK-X6-X7-RESERVED-NEXT: {{  $}}
  ; CHECK-X6-X7-RESERVED-NEXT:   $x28 = ADDI $x5, 0
  ; CHECK-X6-X7-RESERVED-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x10, implicit $x11, implicit $x28
  ; CHECK-X6-X7-RESERVED-NEXT:   $x5 = ADDI $x28, 0
  ; CHECK-X6-X7-RESERVED-NEXT:   PseudoBR %bb.1
  ; CHECK-X6-X7-RESERVED-NEXT: {{  $}}
  ; CHECK-X6-X7-RESERVED-NEXT: bb.1:
  ; CHECK-X6-X7-RESERVED-NEXT:   liveins: $x5, $x14
  ; CHECK-X6-X7-RESERVED-NEXT: {{  $}}
  ; CHECK-X6-X7-RESERVED-NEXT:   $x10 = ADD $x14, $x5
  ; CHECK-X6-X7-RESERVED-NEXT:   PseudoRET implicit $x10

  bb.0:
    liveins: $x10, $x11, $x5
    $x11 = ANDI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x14 = SUB $x10, $x11
    $x11 = ANDI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x14 = SUB $x10, $x11
    PseudoBR %bb.1

  bb.1:
    liveins: $x5, $x14
    $x10 = ADD $x14, $x5
    PseudoRET implicit $x10
...
---
name:            outline_x5_live_reserved_1
tracksRegLiveness: true
body:             |
  ; CHECK-X6-RESERVED-LABEL: name: outline_x5_live_reserved_1
  ; CHECK-X6-RESERVED: bb.0:
  ; CHECK-X6-RESERVED-NEXT:   liveins: $x10, $x11, $x5
  ; CHECK-X6-RESERVED-NEXT: {{  $}}
  ; CHECK-X6-RESERVED-NEXT:   $x7 = ADDI $x5, 0
  ; CHECK-X6-RESERVED-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x7, implicit $x10, implicit $x11
  ; CHECK-X6-RESERVED-NEXT:   $x5 = ADDI $x7, 0
  ; CHECK-X6-RESERVED-NEXT:   PseudoBR %bb.1
  ; CHECK-X6-RESERVED-NEXT: {{  $}}
  ; CHECK-X6-RESERVED-NEXT: bb.1:
  ; CHECK-X6-RESERVED-NEXT:   liveins: $x5, $x14
  ; CHECK-X6-RESERVED-NEXT: {{  $}}
  ; CHECK-X6-RESERVED-NEXT:   $x10 = ADD $x14, $x5
  ; CHECK-X6-RESERVED-NEXT:   PseudoRET implicit $x10
  ;
  ; CHECK-X6-X7-RESERVED-LABEL: name: outline_x5_live_reserved_1
  ; CHECK-X6-X7-RESERVED: bb.0:
  ; CHECK-X6-X7-RESERVED-NEXT:   liveins: $x10, $x11, $x5
  ; CHECK-X6-X7-RESERVED-NEXT: {{  $}}
  ; CHECK-X6-X7-RESERVED-NEXT:   $x28 = ADDI $x5, 0
  ; CHECK-X6-X7-RESERVED-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x10, implicit $x11, implicit $x28
  ; CHECK-X6-X7-RESERVED-NEXT:   $x5 = ADDI $x28, 0
  ; CHECK-X6-X7-RESERVED-NEXT:   PseudoBR %bb.1
  ; CHECK-X6-X7-RESERVED-NEXT: {{  $}}
  ; CHECK-X6-X7-RESERVED-NEXT: bb.1:
  ; CHECK-X6-X7-RESERVED-NEXT:   liveins: $x5, $x14
  ; CHECK-X6-X7-RESERVED-NEXT: {{  $}}
  ; CHECK-X6-X7-RESERVED-NEXT:   $x10 = ADD $x14, $x5
  ; CHECK-X6-X7-RESERVED-NEXT:   PseudoRET implicit $x10


  bb.0:
    liveins: $x10, $x11, $x5
    $x11 = ANDI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x14 = SUB $x10, $x11
    $x11 = ANDI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x14 = SUB $x10, $x11
    PseudoBR %bb.1

  bb.1:
    liveins: $x5, $x14
    $x10 = ADD $x14, $x5
    PseudoRET implicit $x10
...
---
name:            outline_x5_live_reserved_2
tracksRegLiveness: true
body:             |
  ; CHECK-X6-RESERVED-LABEL: name: outline_x5_live_reserved_2
  ; CHECK-X6-RESERVED: bb.0:
  ; CHECK-X6-RESERVED-NEXT:   liveins: $x10, $x11, $x5
  ; CHECK-X6-RESERVED-NEXT: {{  $}}
  ; CHECK-X6-RESERVED-NEXT:   $x7 = ADDI $x5, 0
  ; CHECK-X6-RESERVED-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x7, implicit $x10, implicit $x11
  ; CHECK-X6-RESERVED-NEXT:   $x5 = ADDI $x7, 0
  ; CHECK-X6-RESERVED-NEXT:   PseudoBR %bb.1
  ; CHECK-X6-RESERVED-NEXT: {{  $}}
  ; CHECK-X6-RESERVED-NEXT: bb.1:
  ; CHECK-X6-RESERVED-NEXT:   liveins: $x5, $x14
  ; CHECK-X6-RESERVED-NEXT: {{  $}}
  ; CHECK-X6-RESERVED-NEXT:   $x10 = ADD $x14, $x5
  ; CHECK-X6-RESERVED-NEXT:   PseudoRET implicit $x10
  ;
  ; CHECK-X6-X7-RESERVED-LABEL: name: outline_x5_live_reserved_2
  ; CHECK-X6-X7-RESERVED: bb.0:
  ; CHECK-X6-X7-RESERVED-NEXT:   liveins: $x10, $x11, $x5
  ; CHECK-X6-X7-RESERVED-NEXT: {{  $}}
  ; CHECK-X6-X7-RESERVED-NEXT:   $x28 = ADDI $x5, 0
  ; CHECK-X6-X7-RESERVED-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x10, implicit $x11, implicit $x28
  ; CHECK-X6-X7-RESERVED-NEXT:   $x5 = ADDI $x28, 0
  ; CHECK-X6-X7-RESERVED-NEXT:   PseudoBR %bb.1
  ; CHECK-X6-X7-RESERVED-NEXT: {{  $}}
  ; CHECK-X6-X7-RESERVED-NEXT: bb.1:
  ; CHECK-X6-X7-RESERVED-NEXT:   liveins: $x5, $x14
  ; CHECK-X6-X7-RESERVED-NEXT: {{  $}}
  ; CHECK-X6-X7-RESERVED-NEXT:   $x10 = ADD $x14, $x5
  ; CHECK-X6-X7-RESERVED-NEXT:   PseudoRET implicit $x10


  bb.0:
    liveins: $x10, $x11, $x5
    $x11 = ANDI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x14 = SUB $x10, $x11
    $x11 = ANDI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x14 = SUB $x10, $x11
    PseudoBR %bb.1

  bb.1:
    liveins: $x5, $x14
    $x10 = ADD $x14, $x5
    PseudoRET implicit $x10
...