# REQUIRES: asserts
# RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \
# RUN:   -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \
# RUN:   -mattr=+fusion-logic-reg-reg | FileCheck %s

# Test logic register-register fusion: AND/OR/XOR + AND/OR/XOR
# This fusion combines two consecutive logic operations on registers.

# CHECK: and_or
# CHECK: Macro fuse: {{.*}}AND - OR
---
name: and_or
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11, $x12
    %1:gpr = COPY $x10
    %2:gpr = COPY $x11
    %3:gpr = COPY $x12
    %4:gpr = AND %1, %2
    %5:gpr = XORI %3, 3
    %6:gpr = OR %4, %3
    $x10 = COPY %5
    $x11 = COPY %6
    PseudoRET
...

# CHECK: xor_and
# CHECK: Macro fuse: {{.*}}XOR - AND
---
name: xor_and
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11, $x12
    %1:gpr = COPY $x10
    %2:gpr = COPY $x11
    %3:gpr = COPY $x12
    %4:gpr = XOR %1, %2
    %5:gpr = XORI %3, 3
    %6:gpr = AND %4, %3
    $x10 = COPY %5
    $x11 = COPY %6
    PseudoRET
...

# CHECK: or_xor
# CHECK: Macro fuse: {{.*}}OR - XOR
---
name: or_xor
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11, $x12
    %1:gpr = COPY $x10
    %2:gpr = COPY $x11
    %3:gpr = COPY $x12
    %4:gpr = OR %1, %2
    %5:gpr = XORI %3, 3
    %6:gpr = XOR %4, %3
    $x10 = COPY %5
    $x11 = COPY %6
    PseudoRET
...