; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-p,+m,+zbb \
; RUN:   -verify-machineinstrs < %s | \
; RUN:   FileCheck --check-prefixes=CHECK-RV32 %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb \
; RUN:   -verify-machineinstrs < %s | \
; RUN:   FileCheck --check-prefixes=CHECK-RV64 %s

; Regression test: combinePExtTruncate must not crash when the operand of a
; narrowing shift is not a MUL/SUB (e.g. a plain function argument).

define i32 @trunc_lshr_v2i32_to_v2i16(i64 %a.coerce) {
; CHECK-RV32-LABEL: trunc_lshr_v2i32_to_v2i16:
; CHECK-RV32:       # %bb.0:
; CHECK-RV32-NEXT:    psrli.dw a0, a0, 8
; CHECK-RV32-NEXT:    pack a0, a0, a1
; CHECK-RV32-NEXT:    ret
;
; CHECK-RV64-LABEL: trunc_lshr_v2i32_to_v2i16:
; CHECK-RV64:       # %bb.0:
; CHECK-RV64-NEXT:    psrli.w a0, a0, 8
; CHECK-RV64-NEXT:    srli a1, a0, 32
; CHECK-RV64-NEXT:    ppaire.h a0, a0, a1
; CHECK-RV64-NEXT:    ret
  %v = bitcast i64 %a.coerce to <2 x i32>
  %shr = lshr <2 x i32> %v, splat (i32 8)
  %conv = trunc <2 x i32> %shr to <2 x i16>
  %ret = bitcast <2 x i16> %conv to i32
  ret i32 %ret
}

define i32 @trunc_ashr_v2i32_to_v2i16(i64 %a.coerce) {
; CHECK-RV32-LABEL: trunc_ashr_v2i32_to_v2i16:
; CHECK-RV32:       # %bb.0:
; CHECK-RV32-NEXT:    psrli.dw a0, a0, 8
; CHECK-RV32-NEXT:    pack a0, a0, a1
; CHECK-RV32-NEXT:    ret
;
; CHECK-RV64-LABEL: trunc_ashr_v2i32_to_v2i16:
; CHECK-RV64:       # %bb.0:
; CHECK-RV64-NEXT:    psrli.w a0, a0, 8
; CHECK-RV64-NEXT:    srli a1, a0, 32
; CHECK-RV64-NEXT:    ppaire.h a0, a0, a1
; CHECK-RV64-NEXT:    ret
  %v = bitcast i64 %a.coerce to <2 x i32>
  %shr = ashr <2 x i32> %v, splat (i32 8)
  %conv = trunc <2 x i32> %shr to <2 x i16>
  %ret = bitcast <2 x i16> %conv to i32
  ret i32 %ret
}

define i32 @trunc_lshr_v4i16_to_v4i8(i64 %a.coerce) {
; CHECK-RV32-LABEL: trunc_lshr_v4i16_to_v4i8:
; CHECK-RV32:       # %bb.0:
; CHECK-RV32-NEXT:    psrli.dh a0, a0, 4
; CHECK-RV32-NEXT:    srli a3, a1, 16
; CHECK-RV32-NEXT:    srli a2, a0, 16
; CHECK-RV32-NEXT:    ppaire.db a0, a0, a2
; CHECK-RV32-NEXT:    pack a0, a0, a1
; CHECK-RV32-NEXT:    ret
;
; CHECK-RV64-LABEL: trunc_lshr_v4i16_to_v4i8:
; CHECK-RV64:       # %bb.0:
; CHECK-RV64-NEXT:    psrli.h a0, a0, 4
; CHECK-RV64-NEXT:    srli a1, a0, 48
; CHECK-RV64-NEXT:    srli a2, a0, 32
; CHECK-RV64-NEXT:    ppaire.b a1, a2, a1
; CHECK-RV64-NEXT:    srli a2, a0, 16
; CHECK-RV64-NEXT:    ppaire.b a0, a0, a2
; CHECK-RV64-NEXT:    ppaire.h a0, a0, a1
; CHECK-RV64-NEXT:    ret
  %v = bitcast i64 %a.coerce to <4 x i16>
  %shr = lshr <4 x i16> %v, splat (i16 4)
  %conv = trunc <4 x i16> %shr to <4 x i8>
  %ret = bitcast <4 x i8> %conv to i32
  ret i32 %ret
}