; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64x,+experimental-zvdot4a8i \
; RUN:   -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+experimental-zvdot4a8i \
; RUN:   -verify-machineinstrs | FileCheck %s

; vdot4a.vv - commutable
define <vscale x 2 x i32> @commutable_vdot4a_vv(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: commutable_vdot4a_vv:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT:    vdot4a.vv v8, v8, v9
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vadd.vv v8, v8, v8
; CHECK-NEXT:    ret
entry:
  %a = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32(
    <vscale x 2 x i32> poison,
    <vscale x 2 x i32> %0,
    <vscale x 2 x i32> %1,
    iXLen %2, iXLen 1)
  %b = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32(
    <vscale x 2 x i32> poison,
    <vscale x 2 x i32> %1,
    <vscale x 2 x i32> %0,
    iXLen %2, iXLen 1)
  %ret = add <vscale x 2 x i32> %a, %b
  ret <vscale x 2 x i32> %ret
}

define <vscale x 2 x i32> @commutable_vdot4a_vv_masked(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %mask, iXLen %2) {
; CHECK-LABEL: commutable_vdot4a_vv_masked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT:    vdot4a.vv v8, v8, v9, v0.t
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vadd.vv v8, v8, v8
; CHECK-NEXT:    ret
  %a = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32(
    <vscale x 2 x i32> poison,
    <vscale x 2 x i32> %0,
    <vscale x 2 x i32> %1,
    <vscale x 2 x i1> %mask,
    iXLen %2, iXLen 1)
  %b = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32(
    <vscale x 2 x i32> poison,
    <vscale x 2 x i32> %1,
    <vscale x 2 x i32> %0,
    <vscale x 2 x i1> %mask,
    iXLen %2, iXLen 1)
  %ret = add <vscale x 2 x i32> %a, %b
  ret <vscale x 2 x i32> %ret
}

; vdot4au.vv - commutable
define <vscale x 2 x i32> @commutable_vdot4au_vv(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: commutable_vdot4au_vv:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT:    vdot4au.vv v8, v8, v9
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vadd.vv v8, v8, v8
; CHECK-NEXT:    ret
entry:
  %a = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32(
    <vscale x 2 x i32> poison,
    <vscale x 2 x i32> %0,
    <vscale x 2 x i32> %1,
    iXLen %2, iXLen 1)
  %b = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32(
    <vscale x 2 x i32> poison,
    <vscale x 2 x i32> %1,
    <vscale x 2 x i32> %0,
    iXLen %2, iXLen 1)
  %ret = add <vscale x 2 x i32> %a, %b
  ret <vscale x 2 x i32> %ret
}

define <vscale x 2 x i32> @commutable_vdot4au_vv_masked(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %mask, iXLen %2) {
; CHECK-LABEL: commutable_vdot4au_vv_masked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT:    vdot4au.vv v8, v8, v9, v0.t
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vadd.vv v8, v8, v8
; CHECK-NEXT:    ret
  %a = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32(
    <vscale x 2 x i32> poison,
    <vscale x 2 x i32> %0,
    <vscale x 2 x i32> %1,
    <vscale x 2 x i1> %mask,
    iXLen %2, iXLen 1)
  %b = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32(
    <vscale x 2 x i32> poison,
    <vscale x 2 x i32> %1,
    <vscale x 2 x i32> %0,
    <vscale x 2 x i1> %mask,
    iXLen %2, iXLen 1)
  %ret = add <vscale x 2 x i32> %a, %b
  ret <vscale x 2 x i32> %ret
}

; vdot4asu.vv - NOT commutable (signed x unsigned, operand order matters)
define <vscale x 2 x i32> @commutable_vdot4asu_vv(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: commutable_vdot4asu_vv:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT:    vdot4asu.vv v10, v8, v9
; CHECK-NEXT:    vdot4asu.vv v8, v9, v8
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vadd.vv v8, v10, v8
; CHECK-NEXT:    ret
entry:
  %a = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32(
    <vscale x 2 x i32> poison,
    <vscale x 2 x i32> %0,
    <vscale x 2 x i32> %1,
    iXLen %2, iXLen 1)
  %b = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32(
    <vscale x 2 x i32> poison,
    <vscale x 2 x i32> %1,
    <vscale x 2 x i32> %0,
    iXLen %2, iXLen 1)
  %ret = add <vscale x 2 x i32> %a, %b
  ret <vscale x 2 x i32> %ret
}