; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv32 -mattr=+v < %s | FileCheck %s -check-prefix=RV32
; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s -check-prefix=RV64

; WITH VSCALE RANGE

define i32 @ctz_nxv4i32(<vscale x 4 x i32> %a) #0 {
; RV32-LABEL: ctz_nxv4i32:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; RV32-NEXT:    vmsne.vi v10, v8, 0
; RV32-NEXT:    vfirst.m a0, v10
; RV32-NEXT:    bgez a0, .LBB0_2
; RV32-NEXT:  # %bb.1:
; RV32-NEXT:    csrr a0, vlenb
; RV32-NEXT:    srli a0, a0, 1
; RV32-NEXT:  .LBB0_2:
; RV32-NEXT:    ret
;
; RV64-LABEL: ctz_nxv4i32:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; RV64-NEXT:    vmsne.vi v10, v8, 0
; RV64-NEXT:    vfirst.m a0, v10
; RV64-NEXT:    bgez a0, .LBB0_2
; RV64-NEXT:  # %bb.1:
; RV64-NEXT:    csrr a0, vlenb
; RV64-NEXT:    srli a0, a0, 1
; RV64-NEXT:  .LBB0_2:
; RV64-NEXT:    ret
  %res = call i32 @llvm.experimental.cttz.elts.i32.nxv4i32(<vscale x 4 x i32> %a, i1 0)
  ret i32 %res
}

; NO VSCALE RANGE

define i64 @ctz_nxv8i1_no_range(<vscale x 8 x i16> %a) {
; RV32-LABEL: ctz_nxv8i1_no_range:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
; RV32-NEXT:    vmsne.vi v10, v8, 0
; RV32-NEXT:    vfirst.m a0, v10
; RV32-NEXT:    bgez a0, .LBB1_2
; RV32-NEXT:  # %bb.1:
; RV32-NEXT:    csrr a0, vlenb
; RV32-NEXT:  .LBB1_2:
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    ret
;
; RV64-LABEL: ctz_nxv8i1_no_range:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
; RV64-NEXT:    vmsne.vi v10, v8, 0
; RV64-NEXT:    vfirst.m a0, v10
; RV64-NEXT:    bgez a0, .LBB1_2
; RV64-NEXT:  # %bb.1:
; RV64-NEXT:    csrr a0, vlenb
; RV64-NEXT:  .LBB1_2:
; RV64-NEXT:    ret
  %res = call i64 @llvm.experimental.cttz.elts.i64.nxv8i16(<vscale x 8 x i16> %a, i1 0)
  ret i64 %res
}

define i32 @ctz_nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
; RV32-LABEL: ctz_nxv16i1:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
; RV32-NEXT:    vfirst.m a0, v8
; RV32-NEXT:    bgez a0, .LBB2_2
; RV32-NEXT:  # %bb.1:
; RV32-NEXT:    csrr a0, vlenb
; RV32-NEXT:    slli a0, a0, 1
; RV32-NEXT:  .LBB2_2:
; RV32-NEXT:    ret
;
; RV64-LABEL: ctz_nxv16i1:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
; RV64-NEXT:    vfirst.m a0, v8
; RV64-NEXT:    bgez a0, .LBB2_2
; RV64-NEXT:  # %bb.1:
; RV64-NEXT:    csrr a0, vlenb
; RV64-NEXT:    slli a0, a0, 1
; RV64-NEXT:  .LBB2_2:
; RV64-NEXT:    ret
  %res = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1(<vscale x 16 x i1> %a, i1 0)
  ret i32 %res
}

define i64 @i64_ctz_nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
; RV32-LABEL: i64_ctz_nxv16i1:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
; RV32-NEXT:    vfirst.m a0, v8
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    ret
;
; RV64-LABEL: i64_ctz_nxv16i1:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
; RV64-NEXT:    vfirst.m a0, v8
; RV64-NEXT:    ret
  %res = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1(<vscale x 16 x i1> %a, i1 1)
  ret i64 %res
}

define i64 @i64_ctz_nxv16i1_range(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) vscale_range(2, 1024) {
; RV32-LABEL: i64_ctz_nxv16i1_range:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
; RV32-NEXT:    vfirst.m a0, v8
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    ret
;
; RV64-LABEL: i64_ctz_nxv16i1_range:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
; RV64-NEXT:    vfirst.m a0, v8
; RV64-NEXT:    ret
  %res = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1(<vscale x 16 x i1> %a, i1 1)
  ret i64 %res
}

define i32 @ctz_nxv16i1_poison(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
; RV32-LABEL: ctz_nxv16i1_poison:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
; RV32-NEXT:    vfirst.m a0, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: ctz_nxv16i1_poison:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
; RV64-NEXT:    vfirst.m a0, v8
; RV64-NEXT:    ret
  %res = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1(<vscale x 16 x i1> %a, i1 1)
  ret i32 %res
}

define i32 @ctz_v16i1(<16 x i1> %pg, <16 x i1> %a) {
; RV32-LABEL: ctz_v16i1:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT:    vfirst.m a0, v8
; RV32-NEXT:    bgez a0, .LBB6_2
; RV32-NEXT:  # %bb.1:
; RV32-NEXT:    li a0, 16
; RV32-NEXT:  .LBB6_2:
; RV32-NEXT:    ret
;
; RV64-LABEL: ctz_v16i1:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT:    vfirst.m a0, v8
; RV64-NEXT:    bgez a0, .LBB6_2
; RV64-NEXT:  # %bb.1:
; RV64-NEXT:    li a0, 16
; RV64-NEXT:  .LBB6_2:
; RV64-NEXT:    ret
  %res = call i32 @llvm.experimental.cttz.elts.i32.v16i1(<16 x i1> %a, i1 0)
  ret i32 %res
}

define i32 @ctz_v16i1_poison(<16 x i1> %pg, <16 x i1> %a) {
; RV32-LABEL: ctz_v16i1_poison:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT:    vfirst.m a0, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: ctz_v16i1_poison:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT:    vfirst.m a0, v8
; RV64-NEXT:    ret
  %res = call i32 @llvm.experimental.cttz.elts.i32.v16i1(<16 x i1> %a, i1 1)
  ret i32 %res
}

define i16 @ctz_v8i1_i16_ret(<8 x i1> %a) {
; RV32-LABEL: ctz_v8i1_i16_ret:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT:    vfirst.m a0, v0
; RV32-NEXT:    bgez a0, .LBB8_2
; RV32-NEXT:  # %bb.1:
; RV32-NEXT:    li a0, 8
; RV32-NEXT:  .LBB8_2:
; RV32-NEXT:    ret
;
; RV64-LABEL: ctz_v8i1_i16_ret:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; RV64-NEXT:    vfirst.m a0, v0
; RV64-NEXT:    bgez a0, .LBB8_2
; RV64-NEXT:  # %bb.1:
; RV64-NEXT:    li a0, 8
; RV64-NEXT:  .LBB8_2:
; RV64-NEXT:    ret
  %res = call i16 @llvm.experimental.cttz.elts.i16.v8i1(<8 x i1> %a, i1 0)
  ret i16 %res
}

attributes #0 = { vscale_range(2,1024) }