; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,RV64
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN

define <vscale x 2 x float> @canonicalize_nxv2f32(<vscale x 2 x float> %a) {
; CHECK-LABEL: canonicalize_nxv2f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lui a0, 260096
; CHECK-NEXT:    fmv.w.x fa5, a0
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vfmul.vf v8, v8, fa5
; CHECK-NEXT:    ret
  %r = call <vscale x 2 x float> @llvm.canonicalize.nxv2f32(<vscale x 2 x float> %a)
  ret <vscale x 2 x float> %r
}

define <vscale x 4 x float> @canonicalize_nxv4f32(<vscale x 4 x float> %a) {
; CHECK-LABEL: canonicalize_nxv4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lui a0, 260096
; CHECK-NEXT:    fmv.w.x fa5, a0
; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT:    vfmul.vf v8, v8, fa5
; CHECK-NEXT:    ret
  %r = call <vscale x 4 x float> @llvm.canonicalize.nxv4f32(<vscale x 4 x float> %a)
  ret <vscale x 4 x float> %r
}

define <vscale x 2 x double> @canonicalize_nxv2f64(<vscale x 2 x double> %a) {
; RV32-LABEL: canonicalize_nxv2f64:
; RV32:       # %bb.0:
; RV32-NEXT:    lui a0, %hi(.LCPI2_0)
; RV32-NEXT:    fld fa5, %lo(.LCPI2_0)(a0)
; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32-NEXT:    vfmul.vf v8, v8, fa5
; RV32-NEXT:    ret
;
; RV64-LABEL: canonicalize_nxv2f64:
; RV64:       # %bb.0:
; RV64-NEXT:    li a0, 1023
; RV64-NEXT:    slli a0, a0, 52
; RV64-NEXT:    fmv.d.x fa5, a0
; RV64-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV64-NEXT:    vfmul.vf v8, v8, fa5
; RV64-NEXT:    ret
;
; ZVFHMIN-LABEL: canonicalize_nxv2f64:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    li a0, 1023
; ZVFHMIN-NEXT:    slli a0, a0, 52
; ZVFHMIN-NEXT:    fmv.d.x fa5, a0
; ZVFHMIN-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; ZVFHMIN-NEXT:    vfmul.vf v8, v8, fa5
; ZVFHMIN-NEXT:    ret
  %r = call <vscale x 2 x double> @llvm.canonicalize.nxv2f64(<vscale x 2 x double> %a)
  ret <vscale x 2 x double> %r
}

define <vscale x 4 x half> @canonicalize_nxv4f16(<vscale x 4 x half> %a) {
; ZVFH-LABEL: canonicalize_nxv4f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a0, 15
; ZVFH-NEXT:    slli a0, a0, 10
; ZVFH-NEXT:    fmv.h.x fa5, a0
; ZVFH-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT:    vfmul.vf v8, v8, fa5
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: canonicalize_nxv4f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT:    lui a0, 260096
; ZVFHMIN-NEXT:    fmv.w.x fa5, a0
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT:    vfmul.vf v10, v10, fa5
; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT:    ret
  %r = call <vscale x 4 x half> @llvm.canonicalize.nxv4f16(<vscale x 4 x half> %a)
  ret <vscale x 4 x half> %r
}

define <vscale x 4 x bfloat> @canonicalize_nxv4bf16(<vscale x 4 x bfloat> %a) {
; CHECK-LABEL: canonicalize_nxv4bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT:    lui a0, 260096
; CHECK-NEXT:    fmv.w.x fa5, a0
; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT:    vfmul.vf v10, v10, fa5
; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v10
; CHECK-NEXT:    ret
  %r = call <vscale x 4 x bfloat> @llvm.canonicalize.nxv4bf16(<vscale x 4 x bfloat> %a)
  ret <vscale x 4 x bfloat> %r
}