; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin
;          -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s

define <32 x i1> @fcmp_oeq_vv_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) {
; CHECK-LABEL: fcmp_oeq_vv_v32bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e16, m4, ta, ma
; CHECK-NEXT:    vslidedown.vi v16, v12, 16
; CHECK-NEXT:    vslidedown.vi v20, v8, 16
; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT:    vfwcvtbf16.f.f.v v24, v12
; CHECK-NEXT:    vfwcvtbf16.f.f.v v12, v8
; CHECK-NEXT:    vfwcvtbf16.f.f.v v8, v16
; CHECK-NEXT:    vfwcvtbf16.f.f.v v16, v20
; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT:    vmfeq.vv v20, v16, v8
; CHECK-NEXT:    vmfeq.vv v0, v12, v24
; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT:    vslideup.vi v0, v20, 2
; CHECK-NEXT:    ret
  %c = fcmp oeq <32 x bfloat> %a, %b
  ret <32 x i1> %c
}

define <32 x i1> @fcmp_oeq_vv_v32f16(<32 x half> %a, <32 x half> %b) {
; CHECK-LABEL: fcmp_oeq_vv_v32f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e16, m4, ta, ma
; CHECK-NEXT:    vslidedown.vi v16, v12, 16
; CHECK-NEXT:    vslidedown.vi v20, v8, 16
; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT:    vfwcvt.f.f.v v24, v12
; CHECK-NEXT:    vfwcvt.f.f.v v12, v8
; CHECK-NEXT:    vfwcvt.f.f.v v8, v16
; CHECK-NEXT:    vfwcvt.f.f.v v16, v20
; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT:    vmfeq.vv v20, v16, v8
; CHECK-NEXT:    vmfeq.vv v0, v12, v24
; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT:    vslideup.vi v0, v20, 2
; CHECK-NEXT:    ret
  %c = fcmp oeq <32 x half> %a, %b
  ret <32 x i1> %c
}