; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64

; Make sure we understand that vmv.x.s produces a sign extended
; result and don't have any scalar shifts or ands.

define i1 @test1(<4 x i16> %v) {
; CHECK-LABEL: test1:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT:    vredand.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    addi a0, a0, 1
; CHECK-NEXT:    seqz a0, a0
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %v)
  %cmp = icmp eq i16 %red, -1
  ret i1 %cmp
}

define i1 @test2(<4 x i16> %v) {
; CHECK-LABEL: test2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT:    vredor.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    snez a0, a0
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %v)
  %cmp = icmp ne i16 %red, 0
  ret i1 %cmp
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}}
; RV64: {{.*}}